Double Patterning Gate Layout for Mixed Gate Widths
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Solution Overview
Problem
Current double patterning technologies require additional masks to produce gates of different sizes, which is time-consuming and costly.
Innovation Solution
A method for making gates of different sizes using double patterning technology by forming spacers on sidewalls, applying a silicon-on-carbon layer, and etching to define gate widths with a new mask, allowing for self-aligned processes to merge small, medium, and large-sized gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional masks are introduced to produce gates of different sizes, then gate width variety is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent segments the gate formation process into multiple stages: first forming uniform critical dimension gates using standard double patterning, then selectively removing spacers from specific regions, and finally forming larger gates only where needed. This segmentation allows different gate sizes to be created without requiring additional masks for each size variation.
Solution Approach 2:
The patent performs preliminary actions by forming spacers on all gate structures first, then selectively removing them from regions where larger gates are desired. This preliminary formation of uniform structures followed by selective modification eliminates the need for additional masking steps to create size variations.
2Adaptability or versatility
If additional masks are introduced to produce gates of different sizes, then gate width variety is improved, but manufacturing cost increases
Solution Approach 1:
The process segments gate formation into standard CD gate creation followed by selective spacer removal and localized larger gate formation. This segmentation reuses existing mask patterns and materials, avoiding the need for additional expensive masks while achieving gate width variety.
Solution Approach 2:
The spacers serve multiple functions: they define the critical dimension gates initially, then their selective removal automatically defines where larger gates should form. This self-service approach eliminates the need for additional masks to guide larger gate formation, reducing manufacturing cost.
3Device complexity
If standard double patterning is used, then manufacturing process simplicity is maintained, but gate size variation capability is limited
Solution Approach 1:
The patent performs preliminary formation of uniform spacers on all gate structures using standard double patterning processes. This preliminary action maintains process simplicity while creating the foundation for subsequent gate size variation through selective spacer removal.
Solution Approach 2:
The patent adds a temporal dimension to the standard double patterning process by introducing a selective removal step at an intermediate stage. This additional timing dimension allows gate size variation to be achieved without adding spatial complexity in the form of additional masks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Saves time and reduces costs by enabling the production of gates with varying widths without the need for additional masks, enhancing efficiency in semiconductor manufacturing.
Implementation Method 1
spin-coating an silicon-on-carbon (SOC) layer to cover the spacers of the small-sized gates and cover the large-sized gates
Implementation Method 2
etching the SOC layer and the oxide layer, the etching stops at the upper surface of the hard mask layer, so as to expose the two spacers of at both sides of the dummy gate structures
Data Source
AI summary
The present application provides a method for making gates of different sizes compatible with the double patterning technology, comprising: forming a plurality of dummy gate structures and spacers on the sidewalls; covering the spacers and a region of large-sized gates with an SOC(silicon-on-carbon) layer; etching the SOC layer to expose the spacers of at least one dummy gate structure; respectively forming the first and the second SOC pattern structures, wherein the first SOC pattern structure covers the spacer of at least one dummy gate structure, and the second SOC pattern structure is disposed in region of the large-sized gates; etching the first SOC pattern structure to form a third SOC pattern structure, one side of the third SOC pattern structure covers one side of the spacer, wherein the other uncovered side of the spacer is used to define one side of the gate of medium-sized width.