Double Patterning Insert Pattern Formation for Semiconductor Symmetry
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional double patterning methods in semiconductor device manufacturing face challenges in forming an even number of insert patterns between basic patterns, leading to asymmetric structures and undesirable gate operations due to the need for dummy patterns.
Innovation Solution
A method involving the formation of a first material layer, followed by a second material layer with trenches, and the use of hardmask layer patterns to alternate between first and second insert patterns, ensuring an even number of insert patterns are formed between basic patterns by adjusting etch selectivity and pattern dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional double patterning method is used to form insert patterns, then pattern formation is achieved, but an odd number of insert patterns is formed causing asymmetric structure
Solution Approach 1:
The patent applies preliminary action by forming a mandrel pattern with predetermined spacing before the actual insert patterns. This mandrel serves as a template that guides the subsequent formation of an even number of insert patterns, ensuring symmetric structure from the beginning of the process rather than attempting to correct asymmetry later.
Solution Approach 2:
The patent segments the pattern formation process into distinct stages: first forming the mandrel pattern, then forming insert patterns in between the mandrels, and finally removing the mandrels. This segmentation allows independent control of each step, ensuring that an even number of insert patterns are formed symmetrically between pairs of mandrels.
2Shape
If dummy patterns are added to achieve even number of insert patterns, then symmetric structure is achieved, but device complexity increases
Solution Approach 1:
The patent makes the mandrel patterns multi-functional: they serve as spacing guides during insert pattern formation, as etch masks during the formation process, and are subsequently removed to leave clean insert patterns. This eliminates the need for separate dummy patterns while maintaining structural symmetry.
Solution Approach 2:
The mandrel patterns are temporarily introduced to enable symmetric insert pattern formation, then deliberately removed after serving their purpose. This temporary structure allows the achievement of symmetry without permanent complexity in the final device structure.
3Productivity
If feature size is reduced for high integration, then device integration increases, but photolithography resolution limits are reached
Solution Approach 1:
The patent transitions from direct single-step photolithography to a multi-step self-aligned patterning process. By using vertical mandrel structures and sequential etching steps, the method achieves sub-lithographic resolution, effectively adding a temporal and dimensional dimension to the patterning process to overcome resolution limits.
Solution Approach 2:
The mandrel patterns serve as intermediary structures that enable the formation of finer insert patterns. Instead of directly patterning the final fine features, the mandrels act as intermediate templates that guide the formation of even smaller features through self-aligned etching, effectively mediating between lithography capabilities and final pattern dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of an even number of insert patterns between basic patterns, reducing asymmetry and improving the symmetry of semiconductor device structures, thereby enhancing gate operation performance.
Implementation Method 1
using the hardmask layer patterns as an etching mask to etch the first pattern of the second material layer to expose the first material layer
Data Source
AI summary
A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.


