Double Patterning Metal Gate Critical Dimension Control
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Solution Overview
Problem
Conventional double patterning processes in semiconductor manufacturing cannot form metal gates with different critical dimensions, which is necessary to meet electrical requirements for semiconductor devices like FinFETs.
Innovation Solution
A method involving the formation of a dummy gate layer with a doped portion having etching selectivity, allowing for the creation of first and second dummy gates with different widths, which are then replaced with metal gates of varying dimensions to meet specific electrical requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional double patterning process is used, then manufacturing simplicity is maintained, but the ability to form metal gates with different critical dimensions is lost
Solution Approach 1:
The patent introduces a doped portion within the dummy gate layer that has different etching properties compared to the undoped portion. This local differentiation allows the etching process to selectively remove material at different rates, enabling the formation of metal gates with different critical dimensions from a single dummy gate layer structure.
Solution Approach 2:
The dummy gate layer is divided into distinct regions: a doped portion and an undoped portion. This segmentation allows each region to be etched differently during the self-aligned double patterning process, creating the desired variation in metal gate critical dimensions while maintaining the overall double patterning workflow.
2Manufacturing precision
If dummy gate layer with doped portion is formed, then metal gates with different critical dimensions can be created, but manufacturing process becomes more complex
Solution Approach 1:
The patent changes the physical-chemical parameters of the dummy gate layer by introducing dopants into specific portions. This parameter change (doping concentration) creates etching selectivity between different regions, enabling precise control over the critical dimensions of the resulting metal gates through the self-aligned double patterning etch process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of semiconductor devices with metal gates of distinct critical dimensions, enhancing the performance of semiconductor devices by meeting electrical requirements.
Implementation Method 1
the first doped portion is formed to have an etching selectivity with respect to the other portion of the dummy gate layer
Data Source
AI summary
In a method for manufacturing a semiconductor device, a dummy gate layer and a hard mask layer are sequentially formed on a substrate. A first doped portion is formed in the dummy gate layer, and has an etching selectivity with respect to the other portion of the dummy gate layer. Etching masks are formed on portions of the hard mask layer. The hard mask layer and the dummy gate layer are etched to pattern the first doped portion and the other portion of the dummy gate layer into first dummy gates and second dummy gates. The first dummy gates and the second dummy gates have different widths. A dielectric layer is formed to peripherally enclose each of the first dummy gates and each of the second dummy gates. The first dummy gates and the second dummy gates are replaced with first metal gates and second metal gates.