Double Patterning Overlay Correction Using Aligned Reticle Marks
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Solution Overview
Problem
Conventional lithography processes face challenges in achieving precise alignment and pattern resolution due to the miniaturization of semiconductor devices, leading to incorrect pattern development on wafers with insufficient gaps between interconnect patterns, which is exacerbated by the limitations of current exposure tools and measurement techniques in double patterning processes.
Innovation Solution
A method involving a double patterning process where three reticles are used to form overlapping patterns, with alignment marks allowing for the calculation of overlay correction values to achieve accurate alignment and pattern formation, either by aligning a third reticle to both alignment marks or individually to each mark, and trading off correction values to obtain a compromising correction for forming a third pattern that overlaps both initial patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography processes are used with current infrastructures, then manufacturing simplicity is maintained, but pattern resolution and alignment precision deteriorate due to the miniaturization of semiconductor devices
Solution Approach 1:
The patent applies segmentation by dividing a single complex lithography process into multiple simpler steps through double patterning. The first reticle forms a first pattern, the second reticle forms a second pattern, and these are combined to achieve higher resolution than any single reticle could provide alone. This segmentation allows each reticle to work within achievable resolution limits while the combination achieves the required miniaturization.
Solution Approach 2:
The patent introduces alignment marks as intermediary elements that facilitate precise alignment between patterns formed by different reticles. These alignment marks serve as reference points that enable the measurement and correction of overlay errors, acting as mediators between the lithography process and the final pattern accuracy.
2Manufacturing precision
If double patterning technique is used to increase half-pitch resolution, then pattern resolution improves by up to 200%, but alignment precision deteriorates due to insufficient gaps between interconnect patterns
Solution Approach 1:
The patent uses alignment marks as intermediary reference elements that enable precise measurement and correction of alignment errors. By providing dedicated alignment targets separate from the interconnect patterns, the system can measure overlay errors without being constrained by the insufficient gaps between interconnect patterns, thus maintaining both high resolution and high alignment precision.
Solution Approach 2:
The patent implements feedback through overlay error measurement and correction. Alignment marks are used to measure the actual alignment between patterns, and these measurements feed back into the process to determine correction values. These correction values are then applied to subsequent lithography steps to compensate for measured errors, creating a closed-loop system that maintains precision.
3Measurement precision
If conventional optical overlay targets and measurement techniques are used, then measurement simplicity is maintained, but alignment accuracy deteriorates in double patterning processes
Solution Approach 1:
The patent introduces dedicated alignment marks as intermediary measurement targets that are specifically designed for accurate overlay measurement in double patterning. These alignment marks serve as intermediaries between the complex double patterning process and the measurement system, providing clear, well-defined targets that enable high-precision measurement without requiring complex measurement techniques.
Solution Approach 2:
The patent segments the measurement function by separating alignment measurement from interconnect pattern formation. Alignment marks are distinct, dedicated measurement targets that are measured separately using specialized techniques, while the interconnect patterns are formed separately. This segmentation allows each to be optimized independently, achieving high alignment accuracy without unnecessarily complicating the overall process.
Data Source
AI summary
A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern and a first alignment mark and a second reticle is used to form a second pattern and a second alignment mark in a same layer. A third reticle is aligned to the first alignment mark and the second alignment mark, to obtain an overlay correction value; additionally, a third reticle is aligned to the first alignment mark to obtain a first overlay correction value, a third reticle is aligned to the second alignment mark to obtain a second overlay correction value, and a total overlay correction value is obtained by trading off the first overlay correction value and the second overlay correction value. The third reticle is used to form a third pattern by aligning the third reticle with the total overlay correction value.