Double Patterning Spacer Fabrication for Irregular IC Patterns
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Solution Overview
Problem
Current semiconductor technologies face challenges in fabricating irregular patterns using double patterning techniques, which are essential for advanced integrated circuit (IC) designs with small feature sizes, as they lack an effective method to achieve complex geometries.
Innovation Solution
A method involving the formation of a mandrel pattern, followed by the creation of spacer patterns and subsequent etching processes, allows for the fabrication of irregular patterns by adjusting mask and processing parameters, enabling the formation of complex IC structures like fin-like active regions and trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning is used to form features with small pitch, then manufacturing precision is improved, but the ability to fabricate irregular patterns is lost
Solution Approach 1:
The patent segments the pattern formation process into multiple discrete steps: forming mandrels with a first pitch, depositing spacers, selectively removing portions, and repeating the process. This segmentation allows irregular patterns to be constructed from regular components, achieving both small feature sizes and complex geometries through the method described in claims 1-10
Solution Approach 2:
The patent introduces a temporal dimension to the pattern formation process by using sequential processing steps rather than attempting to form the entire pattern in a single lithography exposure. This allows the system to achieve irregular 2D patterns through a series of 1D spacer depositions and selective removals, effectively using time as an additional degree of freedom
2Manufacturing precision
If advanced IC technologies with smaller feature sizes are implemented, then manufacturing precision is improved, but fabrication complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming mandrels and spacers in advance of the final pattern requirements. The mandrels are formed with dimensions and spacings that are not the final target dimensions, but are instead intermediate structures that will define the final pattern after spacer deposition and selective removal, simplifying the overall process control
Solution Approach 2:
The patent systematically changes geometric parameters between processing steps: mandrel width, spacer thickness, mandrel spacing, and removed portion dimensions are all controlled parameters that can be adjusted to achieve different final patterns. This parameter control approach allows the same basic process flow to produce various irregular patterns at advanced node dimensions
3Adaptability or versatility
If irregular patterns are fabricated using multiple processing steps, then pattern complexity is improved, but manufacturing time increases
Solution Approach 1:
The patent merges multiple pattern formation operations into a unified spacer-based process flow. Rather than using separate lithography and etching steps for each feature, the method combines mandrel formation, spacer deposition, and selective removal into an integrated sequence that can be repeated efficiently, reducing the total number of process cycles required
Solution Approach 2:
The patent uses spacers as copies of the mandrel structures, creating the final pattern as a replica of the intermediate mandrel array. This copying approach allows the same mandrel formation process to be reused multiple times to generate different portions of the final irregular pattern, reducing process variation and improving manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of integrated circuits with irregular patterns and complex geometries, improving the capability to create advanced IC designs with smaller feature sizes, reducing fabrication steps, and potentially lowering manufacturing costs.
Implementation Method 1
forming a mandrel pattern on a substrate by a first lithography process
Implementation Method 2
etching the substrate using the second spacer pattern as an etch mask
Data Source
AI summary
The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.