Double-Patterning-Compliant Standard Cell Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Double-patterning technology faces challenges in resolving native conflicts when integrating cells with closely located features, as it requires conflicting decisions on whether features should be in the same or different masks, leading to design-rule violations and optical proximity effects.
Innovation Solution
Implementing a design method where all cells in a row have either all even-number or all odd-number double-patterning full traces, ensuring that features are either all in the same mask or all in different masks to avoid conflicts, and using buffer zones when necessary to maintain minimum same-mask distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double-patterning technology is used to separate closely located features into different masks, then optical proximity effect is reduced, but native conflicts arise when cells are abutted requiring features to be in conflicting mask configurations
Solution Approach 1:
The patent changes the topological parameter of the power rail network by introducing virtual vias (G0 paths) that create alternative routing paths. This transforms the mask assignment problem from a conflicting state to a consistent state by changing how features are connected across cell boundaries, allowing double-patterning to be applied without native conflicts.
Solution Approach 2:
The patent introduces virtual vias as intermediary elements that mediate the connection between power rails in adjacent cells. These virtual vias act as buffer zones that resolve the mask configuration conflict by providing an intermediate routing path that satisfies the minimum distance requirements for double-patterning while maintaining electrical connectivity.
2Area of stationary object
If cells are abutted to reduce chip area, then chip density increases, but design-rule violations occur due to conflicting mask requirements for features at cell boundaries
Solution Approach 1:
The patent extends the routing problem from a two-dimensional planar layout to a three-dimensional structure by introducing virtual vias that traverse through the substrate. This dimensional extension allows power rails to connect across cell boundaries while maintaining the required spatial separation for double-patterning compliance.
Solution Approach 2:
The patent embeds virtual via structures within the cell boundary regions, nesting the via paths within the existing cell geometry. This nesting approach allows the resolution of mask conflicts without expanding the overall cell footprint, maintaining compact chip design while achieving design-rule compliance.
3Quantity of substance
If features are placed closer together to increase feature density, then chip capacity increases, but optical proximity effect causes features to short
Solution Approach 1:
The patent segments the power rail features into two separate mask patterns (M1 and M2) for double-patterning. This segmentation physically separates features that would otherwise be too close, preventing optical proximity effects while maintaining the high feature density required for advanced technology nodes.
Solution Approach 2:
The patent performs preliminary mask assignment and conflict detection during the design stage, identifying and resolving potential optical proximity issues before fabrication. By pre-establishing the double-patterning mask configuration with virtual vias, the design ensures feature isolation is maintained while achieving maximum density.
Data Source
AI summary
A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.