Double Patterning Transistor Alignment Deviation Reduction
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Solution Overview
Problem
In semiconductor devices, the miniaturization of transistors leads to alignment deviations during double patterning, resulting in variations in transistor characteristics such as source-drain diffusion capacitance and gate-contact capacitance, affecting the performance and reliability of logic and analog circuits.
Innovation Solution
The semiconductor device employs a method where two transistors are formed in separate element forming areas with identical sizes, arranged with a specific pitch offset, and their gate electrodes are formed using double patterning with different masks to minimize alignment deviations and stabilize transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning is used to form gate electrodes in separate element forming areas, then alignment deviations occur during photoengraving, but transistor characteristics can be stabilized by arranging areas with specific pitch offset
Solution Approach 1:
The patent divides the transistor formation process into separate element forming areas (first and second element forming areas) that are arranged with a specific pitch offset. This segmentation allows the gate electrodes to be formed in distinct regions, reducing the impact of alignment deviations during double patterning on overall transistor characteristic consistency.
2Area of moving object
If microminiaturization is pursued to reduce electronic apparatus size, then pattern density increases, but adjacent patterns cannot be formed separated from each other by one mask
Solution Approach 1:
The patent transitions from attempting to form all patterns in a single planar layer to utilizing multiple element forming areas arranged in different spatial positions with specific pitch offsets. This dimensional approach allows adjacent patterns to be formed separately while maintaining the miniaturization benefits, as the separation is achieved through spatial distribution rather than单纯的 planar spacing.
Data Source
AI summary
A semiconductor device is provided which suppresses variations in transistor characteristics such as a source-drain diffusion capacitance. A first transistor TRA is formed in a first element forming area EFA as a divided transistor. A second transistor TRB is formed in a second element forming area EFB as another divided transistor. The first element forming area EFA and the second element forming area EFB are set to the same size. The first element forming area EFA and the second element forming area EFB are arranged deviated from each other in an X direction by a length SPL corresponding to the minimum pitch PT of a gate wiring GH.