Double Patterning Decomposition Using Virtual Indicators
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Solution Overview
Problem
Existing double patterning methods in semiconductor manufacturing face challenges in load balancing and addressing design concerns, leading to sub-optimal fabrication results and potential mismatches in critical path circuits due to decomposition processes performed at either the design or fabrication stages.
Innovation Solution
Implementing a partial-colored design that utilizes virtual or pseudo indicators to designate relationships between semiconductor features, ensuring they are assigned to the same or different photomasks based on critical path requirements, thereby minimizing mismatches and optimizing load balancing, using assistant features or markers that do not physically appear on photomasks but guide the decomposition process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decomposition process is performed at the design stage, then design concerns such as critical path mismatches can be addressed, but fabrication issues such as load balancing are ignored leading to sub-optimal fabrication results
Solution Approach 1:
The patent segments the decomposition process into two distinct stages: a design-stage decomposition that addresses critical path mismatches by assigning features to photomasks, and a fabrication-stage load balancing adjustment that optimizes pattern distribution. This segmentation allows each stage to focus on its specific objectives without compromising the other.
Solution Approach 2:
The design-stage decomposition performs preliminary feature assignment to photomasks based on critical path analysis. This preliminary action establishes the foundation for addressing design concerns, while leaving room for subsequent load balancing adjustments during fabrication preparation.
2Ease of manufacture
If decomposition process is performed at the fabrication stage, then load balancing can be optimized, but design concerns such as critical path mismatches cannot be fully addressed
Solution Approach 1:
The patent divides the overall decomposition workflow into separate design-stage and fabrication-stage components. The fabrication-stage process focuses on load balancing by adjusting pattern assignments while preserving the critical path relationships established during design-stage decomposition.
Solution Approach 2:
The fabrication-stage decomposition performs only the necessary load balancing adjustments without completely redoing the critical path analysis. This partial action approach maintains the benefits of design-stage decomposition while adding fabrication optimization.
3Manufacturing precision
If full-colored design is used to address critical path concerns, then design precision is improved, but fabrication complexity increases due to additional constraints
Solution Approach 1:
The patent separates full-colored design (critical path decomposition) from load balancing operations. This segmentation allows the complex critical path analysis to be performed once during design, while fabrication-stage adjustments focus only on simpler load distribution tasks.
Solution Approach 2:
Instead of performing complete decomposition analysis at both design and fabrication stages, the patent applies partial decomposition at the fabrication stage, focusing only on load balancing adjustments. This reduces overall process complexity while maintaining precision where needed.
Data Source
AI summary
Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.