Double-Rate DSP Blocks for FPGA Throughput Bottlenecks
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Solution Overview
Problem
Programmable logic devices like FPGAs face performance limitations due to a lower-rate switching fabric, which restricts the clocking speed of digital signal processing functionalities, necessitating a higher number of DSP resources to operate at lower speeds.
Innovation Solution
Implementing a programmable interconnect that routes input signals at a system clock rate and includes digital signal processor blocks with double-rate capabilities, allowing input signals to be registered and multiplied at multiples of the system clock rate, effectively enabling higher throughput DSP slices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the switching fabric is designed for high routing density to enable programmability, then the device achieves adaptability and programmability, but the system clock rate is limited to lower speeds (e.g., 250 Msps)
Solution Approach 1:
The device is segmented into distinct functional domains: a lower-speed programmable switching fabric for routing and a higher-speed DSP domain for computation. This segmentation allows each domain to operate at its optimal speed without being constrained by the other, resolving the contradiction between programmability and high-speed operation.
Solution Approach 2:
Double-rate registers serve as intermediaries between the switching fabric and DSP blocks. These registers operate at twice the system clock rate and buffer data transferred from the switching fabric, enabling DSP blocks to process data at higher speeds while the switching fabric maintains its lower clock rate for programmability.
2Productivity
If the system clock rate is increased to improve throughput, then the processing speed increases, but the number of required DSP resources (multipliers) must increase to maintain the same computational capacity
Solution Approach 1:
The clock rate parameter of DSP blocks is changed to operate at multiples of the system clock rate (e.g., 2x, 4x, or 8x). This parameter change allows existing multipliers to process more data per unit time, increasing throughput without requiring additional multiplier resources.
3Speed
If DSP slices are enabled to operate at their full speed capability, then the processing speed increases, but the switching fabric becomes a bottleneck limiting data flow to and from the DSP slices
Solution Approach 1:
Double-rate registers perform preliminary buffering of data transferred from the switching fabric before data enters the high-speed DSP blocks. By pre-buffering data at double the system clock rate, the registers prepare the data stream to match the higher processing speed of DSP blocks, preventing the switching fabric from becoming a bottleneck.
Solution Approach 2:
The double-rate registers continuously operate at twice the system clock rate, maintaining an uninterrupted high-speed data stream to DSP blocks. This continuous operation ensures that DSP blocks always have data available at their full processing capacity, maximizing productivity without being constrained by the slower switching fabric.
Data Source
AI summary
A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including: a plurality of input ports; an input register coupled to the multiple input ports and adapted to sequentially register samples of the input signals from the interconnect received at the input ports at a multiple of the system clock rate; and a multiplier adapted to multiply the registered samples at the multiple of the system clock rate to produce an output signal.