Double RESURF LDMOS Shared Mask Implant Process
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Solution Overview
Problem
Conventional double-RESURF LDMOS transistors face challenges in scaling high voltage implants due to the complexity of the boron implant process, requiring extra masks and energy, which limits the optimization of breakdown voltage (BV) and specific resistance (RDSON) characteristics.
Innovation Solution
A method using a shared mask to implant both N-type and P-type buried layers, allowing the P-type implant to form a P-surf region between the N-type buried layer and the N-drift region, thereby enhancing BV and reducing RDSON, while eliminating the need for separate masks and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate masks are used for P-type and N-type buried layer implants, then implant precision can be optimized, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the P-type and N-type buried layer implant masks into a single shared mask structure. The mask contains both a first opening for P-type implant and a second opening for N-type implant, eliminating the need for separate mask fabrication and alignment steps while maintaining precise implant positioning through the shared mask's designed opening geometries.
Solution Approach 2:
The shared mask serves multiple functions simultaneously: it defines the P-type buried layer implant region through the first opening, defines the N-type buried layer implant region through the second opening, and provides a common reference frame for both implants. This multi-functional mask reduces device complexity while preserving manufacturing precision.
2Reliability
If high energy boron implant is used to form P-type buried layer below deep N-well, then breakdown voltage can be enhanced, but process complexity and energy requirements increase
Solution Approach 1:
The patent performs the P-type buried layer implant through the shared mask before forming the deep N-well structure. By establishing the P-type region in advance, the subsequent deep N-well formation and N-type implant processes can proceed without requiring additional high-energy implant steps, thereby enhancing breakdown voltage while reducing overall process complexity.
Solution Approach 2:
The shared mask acts as an intermediary that enables precise delivery of P-type implant material to the desired location below the deep N-well without requiring direct high-energy implantation through complex masking. The mask's opening geometry controls the implant profile, simplifying the process while achieving the required breakdown voltage enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a cost-effective and reliable method for producing double-RESURF LDMOS transistors with improved BV and lower RDSON, facilitating precise positioning and larger implant regions, thus optimizing device performance and reducing manufacturing costs.
Implementation Method 1
the P-type and N-type implant materials are selected, implanted and annealed such that the selected P-type material (e.g., Boron) diffuses into the epitaxial layer at a faster rate than the selected N-type material (e.g., Antimony)
Implementation Method 2
an epitaxial layer is then formed on the base substrate over the separately patterned N-type and P-type diffusions, and then the substrate is annealed such that the P-type and N-type implant materials diffuse upward into the epitaxial layer
Data Source
AI summary
A double-RESURF LDMOS fabrication method utilizes a shared mask to form separately patterned N+ buried layer (NBL) and P+ buried layer (PBL) regions. The mask includes two opening types (e.g., large and small), and the P-type and N-type implant materials are separately directed onto the mask at different implant angles, such that the N-type implant passes through both opening types to form a first pattered implant region in both a first region and a surrounding second region, and such that the P-type implant material passes only through the larger openings and forms a second pattered implant region only in the first substrate portion. An optional epitaxial layer is deposited over the substrate and annealed to form the separately patterned PBL and NBL in the epitaxial layer, where a portion of the PBL diffuses above the NBL and forms a P-surf region below the LDMOS's N-drift region.