Double Rounded Floating-Point Multiply Add Fusion
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Solution Overview
Problem
Modern processors face performance degradation and increased die area issues when implementing fused floating-point multiply-add operations, as well as the need for recompilation and potential power inefficiencies, due to the width and accuracy requirements of floating-point hardware.
Innovation Solution
The implementation of double rounded combined floating-point multiply and add instructions, which fuse FP multiplication and addition operations with rounding, allowing for dynamic fusion at runtime or through recompilation, reducing latency and improving instruction execution efficiency by using overflow detection for precise rounding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If true fused floating-point multiply-add operations are implemented, then improved accuracy is achieved, but die area increases and performance degradation occurs for legacy applications
Solution Approach 1:
The processor is divided into multiple execution units: some with full-width floating-point multipliers and adders for accurate fused operations, and others with narrower multipliers for legacy applications. This segmentation allows different parts of the processor to handle different operation types with appropriate precision and area efficiency.
Solution Approach 2:
The processor dynamically selects which execution unit to use based on the operation type. When a fused multiply-add operation is detected, the full-width unit is used; for legacy operations, the narrower unit is used. This dynamic adaptation allows the processor to optimize between accuracy and area usage based on runtime requirements.
2Measurement precision
If full-width floating-point multipliers and adders are used for fused operations, then accuracy is improved, but performance degradation occurs for legacy applications
Solution Approach 1:
Multiple execution units with different capabilities are provided: full-width units for fused operations and narrower units for legacy operations. This allows parallel execution paths where legacy applications can utilize the narrower, faster units while new applications get the accuracy of full-width units.
Solution Approach 2:
The processor changes the operational parameters (multiplier width, adder width) based on the operation type. For fused multiply-add operations, full-width parameters are used to ensure accuracy; for legacy operations, narrower parameters are used to maintain performance. This parameter adaptation resolves the contradiction between accuracy and performance.
3Measurement precision
If floating-point hardware width is increased to support fused operations, then accuracy is improved, but power consumption increases
Solution Approach 1:
The processor segments its execution units into full-width and narrower variants. The full-width units consume more power but provide higher accuracy for fused operations, while narrower units consume less power for legacy operations. This segmentation allows power-efficient operation for most legacy code while providing high-accuracy paths when needed.
Solution Approach 2:
The hardware parameters (width of multipliers and adders) are changed based on the operation type. Full-width parameters are activated only when fused multiply-add operations are executed, while narrower parameters are used for legacy operations. This dynamic parameter change optimizes the balance between accuracy and power consumption based on actual workload requirements.
Data Source
AI summary
Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.