Double Seal Ring Layout for Flexible Chip Interconnects
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Solution Overview
Problem
Existing seal ring structures in semiconductor technologies do not offer sufficient flexibility to accommodate varying chip architectures, particularly in forming fully closed or partially closed seal rings to optimize chip protection and interconnectivity during the dicing process.
Innovation Solution
A dual seal ring structure is introduced, where an outer seal ring encloses multiple inner seal rings, with the option to selectively open or close inner seal rings for interconnects, and redundant regions are utilized for forming electrical circuits to enhance protection and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single seal ring structure is used, then the manufacturing process is simple, but the flexibility to accommodate varying chip architectures is insufficient
Solution Approach 1:
The seal ring is divided into multiple segments: an outer seal ring and one or more inner seal rings. This segmentation allows each ring to be independently configured - the outer ring can remain closed while inner rings are selectively opened or closed based on chip architecture requirements, providing architectural flexibility without requiring complete redesign of the entire seal ring structure
Solution Approach 2:
Inner seal rings are nested within the outer seal ring structure. This nested configuration allows the inner rings to be selectively opened or closed independently while the outer ring maintains its protective function, enabling adaptation to different chip architectures while maintaining overall structural integrity
2Adaptability or versatility
If inner seal rings are opened for interconnects, then interconnectivity between circuit regions is improved, but protection against moisture and contamination is reduced
Solution Approach 1:
The seal ring protection is segmented into outer and inner rings with different functional roles. The outer seal ring remains closed to provide continuous protection against moisture and contamination, while inner seal rings are selectively opened to enable interconnects, thus distributing the protection and interconnect functions to different segments
Solution Approach 2:
The nested structure allows inner seal rings to be opened for interconnects while the outer seal ring maintains its closed protective barrier. This nested configuration ensures that even when inner rings are opened, the outer ring continues to provide protection against moisture and contamination
3Adaptability or versatility
If redundant regions are utilized for forming electrical circuits, then chip functionality is enhanced, but the number of masks required increases
Solution Approach 1:
The redundant regions between the outer seal ring and inner seal rings are designed to serve multiple functions: they provide structural support for the seal ring configuration, enable formation of electrical circuits to enhance chip functionality, and can be selectively opened or closed based on architectural needs, all while being processed through the existing mask set used for seal ring formation
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.