Double-seal ring structures for scalable semiconductor wafer circuits
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Solution Overview
Problem
Advanced wafer processes using low dielectric constant materials require seal ring structures to prevent crack propagation during dicing, which complicates electrical interconnection of neighbor devices on semiconductor wafers.
Innovation Solution
A processed semiconductor wafer design featuring initial layered elements forming electrical circuits with double-seal ring structures surrounding each circuit, allowing for electrical interconnection and additional layered elements to enhance scalability and mitigate cracking risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If seal ring structures are added to prevent crack propagation during dicing, then reliability is improved, but device complexity increases
Solution Approach 1:
The seal ring structure is divided into multiple segments rather than forming a complete continuous ring. This segmentation allows the structure to prevent crack propagation while reducing the amount of material required and simplifying the fabrication process. The segmented seal rings can be formed using standard interconnect layers without requiring additional processing steps.
Solution Approach 2:
The seal ring structure extends through multiple vertical layers of the wafer, utilizing the third dimension to provide crack prevention. By distributing the seal structure across multiple layers rather than concentrating it in a single plane, the patent achieves effective crack containment while maintaining compatibility with existing multi-layer interconnect architectures.
2Reliability
If seal ring structures are added to prevent crack propagation, then reliability is improved, but ease of manufacture deteriorates
Solution Approach 1:
The seal ring structure serves multiple functions simultaneously: it prevents crack propagation during dicing, provides electrical isolation between adjacent devices, and can serve as part of the interconnect architecture. This multi-functionality eliminates the need for separate dedicated seal ring processing steps, as the same structures perform multiple roles in the device architecture.
Solution Approach 2:
The seal ring structures are merged with the existing interconnect layers and device structures. Rather than adding separate seal ring layers, the patent integrates the seal function into the existing multi-layer interconnect architecture, using conductive and dielectric materials that are already part of the standard fabrication process.
3Productivity
If neighbor devices are electrically interconnected to create scaled products, then productivity is improved, but reliability deteriorates due to increased cracking risk
Solution Approach 1:
The wafer is divided into multiple independently-supported device regions separated by segmented seal rings. This segmentation allows adjacent devices to be electrically interconnected for scaling while each device maintains its own crack containment zone. The segmented structure prevents cracks from one device from propagating to neighboring devices, enabling reliable wafer-level interconnection.
Solution Approach 2:
The seal ring structures act as intermediary elements between adjacent devices, providing both electrical isolation and mechanical support. These intermediary structures allow devices to be electrically connected through controlled interconnect paths while physically isolating them to prevent crack propagation, thus enabling scaling without compromising reliability.
Data Source
AI summary
A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.


