Double-Side Connection Package with Through Electrodes
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Solution Overview
Problem
Conventional wafer level chip size packages require facilities similar to those used in the semiconductor fabrication stage for processes like rewiring and post electrode plating, making it difficult for manufacturers dedicated to the packaging stage to produce chip-size double side electrode packages with external electrodes at positions other than the tip ends of post electrodes.
Innovation Solution
A chip-size double side connection package is manufactured by forming through electrodes in the semiconductor substrate, connecting post electrodes with support portions and front face wiring traces, and exposing these for external connection, allowing for the formation of external electrodes at different positions using low resistance metal and insulation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional wafer level chip size package processes are used, then chip-size double side electrode packages can be manufactured, but facilities similar to semiconductor fabrication stage are required which increases manufacturing complexity and investment cost
Solution Approach 1:
The manufacturing process is segmented into two independent parts: (1) through electrode formation in the semiconductor substrate, and (2) post electrode and wiring trace formation as a separate component. This segmentation allows packaging stage manufacturers to produce the semiconductor substrate with through electrodes using conventional packaging facilities, while the post electrodes and wiring traces can be added as a separate component, eliminating the need for semiconductor fabrication stage facilities.
Solution Approach 2:
The patent introduces an intermediary component (post electrode with wiring trace) that bridges the semiconductor substrate and the external connection needs. This intermediary can be formed and prepared separately using conventional packaging facilities, then attached to the substrate, thereby mediating between the substrate manufacturing and the complex rewiring requirements that previously needed semiconductor fabrication facilities.
2Adaptability or versatility
If external electrodes are positioned at locations other than tip ends of post electrodes, then design flexibility is improved, but manufacturing difficulty increases due to requiring advanced facilities
Solution Approach 1:
The patent makes the electrode configuration dynamic and adaptable by forming wiring traces that can extend from the post electrodes to various locations on the front face of the substrate. This allows external electrodes to be positioned flexibly at different locations rather than being fixed at the tip ends of post electrodes, while the wiring traces can be routed to accommodate any desired position, providing design flexibility without requiring advanced facilities.
Solution Approach 2:
The patent adds a dimensional aspect to electrode connection by extending wiring traces along the front face surface of the substrate. Instead of direct vertical connections at post electrode tips, the wiring traces provide a path along the surface, enabling external electrodes to be positioned at various locations in the planar dimension, thus achieving positioning flexibility through dimensional extension.
3Reliability
If both upper and lower faces are covered with insulation layers, then package testing is facilitated and stacking is enabled, but the area of the completed package increases
Solution Approach 1:
The patent uses thin film insulation layers covering both the upper and lower faces of the substrate. These thin film layers provide the necessary insulation for reliable testing and stacking compatibility while minimizing the increase in package area. The thin film nature allows the insulation function to be achieved with minimal thickness, thus reducing the area penalty.
Solution Approach 2:
The insulation layers are nested within the overall package structure, with the front face insulation layer containing the wiring traces and the back face insulation layer containing the through electrodes. This nesting arrangement allows both faces to be covered with insulation layers for testing and stacking purposes while keeping the overall package area compact, as the insulation layers are integrated into the existing structure rather than adding external bulk.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of chip-size double side connection packages that can be freely combined and stacked, facilitating thorough inspection and easier three-dimensional stacking, while allowing manufacturers to perform processes off-line without large investments in advanced facilities.
Implementation Method 1
Holes corresponding to through electrodes are formed in the semiconductor substrate at the centers of the electrode connection regions or in the vicinity thereof. A low resistance metal is charged into each of the holes to thereby form the through electrodes.
Data Source
AI summary
A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.