Double-Side Contact Transistors for Denser 3DIC Standard Cells
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Solution Overview
Problem
Conventional contact configurations in 3DIC devices, such as FinFET and Gate-All-Around devices, limit the ability for high-density connections in stacked configurations due to restricted access for frontside and backside contacts, hindering the advancement of miniaturization and integration in semiconductor transistors.
Innovation Solution
The implementation of transistors with double-side contacts, where both frontside and backside surfaces of the drain and source regions have silicide layers coupled to respective contact structures, allowing for electrical connections on both sides, thereby enhancing connectivity and reducing the complexity of standard cell configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional contact configurations are used in 3DIC devices, then manufacturing process is simpler, but connectivity density and routing flexibility are limited
Solution Approach 1:
The patent introduces double-side contacts that extend from both the frontside and backside of the semiconductor substrate, utilizing the third dimension (vertical depth) to create additional connection points. This allows signals to be routed from both sides of the chip, effectively doubling the available connection density without increasing lateral footprint, thereby resolving the contradiction between connectivity density and device complexity.
Solution Approach 2:
The contact structure is segmented into frontside contacts and backside contacts, with each side independently configured and routed. This segmentation allows separate optimization of routing paths on each side, increasing overall connectivity flexibility while maintaining manageable complexity through modular design of the contact system.
2Adaptability or versatility
If conventional single-side contacts are used, then cell height is larger, but routing flexibility and porosity are reduced
Solution Approach 1:
By adding backside contacts, the patent utilizes the vertical dimension to route signals through the substrate thickness, allowing shorter lateral routing paths and reducing the required cell height while simultaneously increasing routing flexibility through dual-side access to contact points.
3Adaptability or versatility
If double-side contacts with silicide layers are implemented, then connectivity and routing flexibility are improved, but manufacturing precision requirements increase
Solution Approach 1:
The silicide layers are formed on both frontside and backside surfaces before final alignment and bonding operations. This preliminary formation of contact layers allows for pre-positioning of conductive paths, reducing the precision burden on subsequent alignment steps and facilitating the implementation of double-side contacts while managing manufacturing precision requirements.
Data Source
AI summary
Disclosed are standard cells, transistors, and methods for fabricating the same. In an aspect, a transistor includes a drain and a source each including a first drain/source silicide layer on a frontside surface of the drain/source and a second drain/source silicide layer on a backside surface of the drain/source. The first drain silicide layer is coupled to a first drain contact structure or the second drain silicide layer is coupled to a second drain contact structure. The first source silicide layer is coupled to a first source contact structure or the second source silicide layer is coupled to a second source contact structure. A gate structure is disposed between the source and the drain. A channel is at least partially enclosed by the gate structure and disposed between the source and the drain and is recessed from the backside surfaces of the source and drain.