Double-Sided Semiconductor Die Stacks for Low-Loss 3D Interconnects

Solution Overview

Problem

The increasing complexity of semiconductor packages has led to challenges in reducing ohmic loss and signal delay due to longer interconnect lengths, necessitating improvements in package design to enhance integration and connectivity among components.

Innovation Solution

The use of double-sided semiconductor dies with a central portion formed in a front-end-of-line (FEOL) process, sandwiched between front-side and back-side interconnect structures formed in back-end-of-line (BEOL) processes, allows for optimized performance of individual dies without compromising other dies, enabling efficient die-to-die connections and flexible combinations of different types of semiconductor dies in a chip assembly structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional semiconductor package designs are used to accommodate greater numbers of integrated circuits and dies per package, then package capacity increases, but interconnect lengths increase leading to higher ohmic loss, heat generation, and signal delay

Engineering Contradiction:

Improvenumber of integrated circuits and dies per packageVSAvoidohmic loss

Core Design Contradiction:

Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent transitions from traditional two-dimensional planar packaging to three-dimensional vertical stacking architecture. Multiple semiconductor dies are stacked vertically and interconnected through through-silicon vias (TSVs) and interlayer dielectric structures, enabling high-density integration while maintaining short interconnect lengths between adjacent dies in the vertical dimension.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested interconnection structures where conductive vias are embedded within interlayer dielectric materials, which are themselves embedded within semiconductor dies and packaging structures. This nested arrangement allows multiple interconnection levels to be compactly integrated without increasing overall package footprint or interconnect length.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Quantity of substance

If traditional semiconductor package designs are used to accommodate greater numbers of integrated circuits and dies per package, then package capacity increases, but interconnect lengths increase leading to higher signal delay

Engineering Contradiction:

Improvenumber of integrated circuits and dies per packageVSAvoidsignal delay

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent transitions from traditional two-dimensional planar packaging to three-dimensional vertical stacking architecture. Multiple semiconductor dies are stacked vertically and interconnected through through-silicon vias (TSVs) and interlayer dielectric structures, enabling high-density integration while maintaining short interconnect lengths between adjacent dies in the vertical dimension.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If complex semiconductor packages are designed to integrate more components, then integration capacity increases, but package size increases making interconnections more difficult

Engineering Contradiction:

Improvenumber of integrated circuits and dies per packageVSAvoidpackage size and interconnection complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from traditional two-dimensional planar packaging to three-dimensional vertical stacking architecture. Multiple semiconductor dies are stacked vertically and interconnected through through-silicon vias (TSVs) and interlayer dielectric structures, enabling high-density integration while maintaining short interconnect lengths between adjacent dies in the vertical dimension.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the semiconductor package into discrete stacked dies, each potentially containing specific functional circuits. This segmentation allows independent optimization of each die and flexible reconfiguration of the stack to achieve desired functionality while maintaining compact overall package size.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20240113078A1Three dimensional heterogeneous integration with double-sided semiconductor dies and methods of forming the same

Publication Date: 2024.04.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An embodiment semiconductor device may include a semiconductor die stack having a first semiconductor die including a first front-side interconnect structure and a first back-side interconnect structure, and a second semiconductor die including a second front-side interconnect structure and a second back-side interconnect structure, such that the first back-side interconnect structure is electrically connected to the second front-side interconnect structure. The first semiconductor die may include a first central portion disposed between the first front-side interconnect structure and the first back-side interconnect structure, the second semiconductor die may include a second central portion disposed between the second front-side interconnect structure and the second back-side interconnect structure, and each of the first central portion and second central portion may include electrical circuit elements formed in or on a semiconductor substrate. Each of the first and second front-side interconnect structures and back-side interconnect structures may include interconnects formed within a dielectric layer.