Double-Sided Multichip Packaging with Direct Die Coupling
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Solution Overview
Problem
Existing multichip packaging technologies face challenges in efficiently integrating semiconductor die and other components with different footprints and thicknesses in dense arrangements, while also providing effective electrical interconnects and thermal management.
Innovation Solution
The proposed solution involves a multichip package design that includes a volume of molding material encapsulating multiple electronic components, with upper and lower sets of redistribution layers and through-package interconnects that allow for electrical coupling between components and external contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional multichip packaging methods are used with vias and molding compound, then devices can be protected and interconnected, but the volume required for components increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar 2D packaging to three-dimensional stacking architecture, where multiple semiconductor dies are vertically stacked and interconnected through through-silicon vias (TSVs). This dimensional change enables higher integration density within a reduced footprint volume, directly addressing the contradiction between package volume and component integration.
Solution Approach 2:
The patent implements nested packaging by placing multiple semiconductor dies within each other's vertical space through stacking. The first semiconductor die is positioned at a first level, the second semiconductor die at a second level, with intermediate packaging material nested between them. This nesting approach maximizes space utilization and reduces overall package volume while maintaining protection and interconnection functions.
2Volume of moving object
If multiple devices are assembled within one package to reduce volume, then space is saved, but the requirement for specific die placement and substrate modifications increases
Solution Approach 1:
The patent creates a universal packaging structure using intermediate packaging material that can accommodate semiconductor dies with varying footprints and thicknesses. The intermediate material serves multiple functions: mechanical support, electrical isolation, and stress distribution, enabling flexible arrangement of different device types without requiring substrate modifications. This multi-functional approach directly addresses the contradiction between volume reduction and adaptability.
Solution Approach 2:
The patent employs parameter changes in the intermediate packaging material properties to adapt to different die configurations. By adjusting the material's viscosity, curing characteristics, and mechanical properties, the system can accommodate various die sizes, shapes, and thicknesses within the same packaging structure, enhancing versatility while maintaining compact volume.
3Reliability
If through-dielectric vias are used to interconnect semiconductor dies, then device performance improves, but manufacturing complexity and substrate modifications increase
Solution Approach 1:
The patent extracts the interconnection function from the substrate level and implements it at the die level through TSVs formed directly in the semiconductor dies. By taking out the via formation process from substrate modifications and integrating it into the die structure itself, the patent reduces substrate complexity while maintaining high-performance electrical interconnection between stacked dies.
Solution Approach 2:
The patent introduces conductive material as an intermediary within TSVs to enable direct electrical coupling between semiconductor dies. This intermediary conductive path through the silicon substrate eliminates the need for complex external substrate routing and via structures, simplifying substrate modifications while achieving reliable high-speed interconnection for improved device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of components with varying sizes and thicknesses in a single package, providing enhanced electrical connectivity and flexibility in component arrangement, which improves packaging efficiency and performance.
Implementation Method 1
The first surface of the second electronic component is bonded to the first surface of the first electronic component
Data Source
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AI summary
A multi-chip package includes two electronic components bonded to each other via electrical contacts on corresponding faces of the components that are directly opposite each other. The components are encapsulated in a volume of molding material that includes a upper and lower sets of redistribution layers disposed on upper and lower surfaces of the volume of molding material that include electrical interconnects. The package includes one or more through-package interconnects that pass through the molding material. A first through-package interconnect couples an electrically conductive interconnect in a first redistribution layer to an electrically conductive interconnect in a second redistribution layer on an opposite side of the volume of molding material from the first redistribution layer, or it couples the interconnect to one of the components within the volume of molding material.