Double-Sided Die Interconnect Layout for Shorter Chip Stacking Paths

Solution Overview

Problem

Existing semiconductor die stacking methods involving additional interconnection elements like interposers or TSVs increase cost and complexity, and lengthen die-to-die interconnects.

Innovation Solution

A semiconductor package design where a first die has interconnect layers on both sides, allowing direct coupling to a second die without intervening structures like TSVs, reducing thickness and interconnect length.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional interconnection elements like interposers or TSV structures are used for die to die stacking, then die to die interconnection can be achieved, but cost and complexity increase

Engineering Contradiction:

Improvedie to die interconnectionVSAvoidstacking structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the additional interconnection elements (interposers, TSV structures) from the stacking architecture. By forming interconnect layers directly on both sides of the semiconductor die, the invention removes the need for separate interposition structures, thereby reducing complexity while maintaining interconnection functionality

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the interconnection function into the die structure itself by forming interconnect layers on both the first and second major surfaces of the semiconductor die. This integration combines the die substrate and interconnection elements into a unified structure, eliminating the need for separate interposer components

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If additional interconnection elements like interposers or TSV structures are used for die to die stacking, then die to die interconnection can be achieved, but manufacturing cost increases

Engineering Contradiction:

Improvedie to die interconnectionVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts and eliminates the additional interconnection elements (interposers, TSV structures) from the stacking architecture. By forming interconnect layers directly on both sides of the semiconductor die, the invention removes the need for separate interposition structures, thereby reducing complexity while maintaining interconnection functionality

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive, complex interposer structures with simpler, more cost-effective interconnect layers formed directly on the die surfaces. This substitution uses more economical manufacturing processes while achieving the same interconnection purpose

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Reliability

If additional interconnection elements like interposers or TSV structures are used for die to die stacking, then die to die interconnection can be achieved, but die to die interconnect length increases

Engineering Contradiction:

Improvedie to die interconnectionVSAvoiddie to die interconnect length

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent extracts and eliminates the additional interconnection elements (interposers, TSV structures) from the stacking architecture. By forming interconnect layers directly on both sides of the semiconductor die, the invention removes the need for separate interposition structures, thereby reducing complexity while maintaining interconnection functionality

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent utilizes both major surfaces of the semiconductor die for interconnection purposes, effectively using the third dimension (depth/thickness) to reduce interconnect length. By forming interconnect layers on opposite surfaces, the patent creates direct, short pathways for electrical connections between stacked dies

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12362325B2Monolithic chip stacking using a die with double-sided interconnect layers

Publication Date: 2025.07.15 INTEL CORP

AI summary

An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.