Double-Sided Die Assembly for Dense 3D Interconnect Routing
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Solution Overview
Problem
Current techniques for coupling integrated circuit devices are limited by manufacturing constraints, device size, thermal considerations, and interconnect congestion, which impact costs and implementations, particularly in achieving reliable signal communication and power delivery between small, densely packed dies.
Innovation Solution
The microelectronic assembly employs a double-sided die configuration with conductive contacts on both faces, utilizing die-to-die interconnects and a redistribution layer to facilitate efficient power delivery and signal transmission, while reducing package size and increasing design flexibility through heterogeneous technology integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If current coupling techniques are used for integrated circuit devices, then manufacturing is simpler, but device size increases and thermal management becomes difficult
Solution Approach 1:
The patent transitions from planar (2D) die arrangement to three-dimensional (3D) stacked configuration, stacking dies vertically along the Z-axis to achieve higher integration density without increasing the footprint area. This dimensional change enables compact package size while maintaining manufacturing feasibility through established bonding processes.
Solution Approach 2:
Multiple dies are nested vertically within a compact package structure, with each die stacked above the previous one. The package substrate provides a foundation that supports the stacked dies, creating a nested configuration where smaller components are arranged within the vertical space of the package rather than spreading out horizontally.
2Reliability
If more interconnect contacts are added for signal communication, then bandwidth increases, but interconnect congestion worsens
Solution Approach 1:
Interconnect contacts are arranged in multiple vertical layers corresponding to different die stacking levels. This 3D interconnect architecture allows signals to be routed through vertical vias and horizontal traces across multiple planes, dramatically increasing the number of available interconnect paths without increasing congestion in any single layer.
Solution Approach 2:
The interconnect structure is segmented into multiple functional layers: first-level interconnects for die-to-package-substrate connections, second-level interconnects for die-to-die connections, and redistribution layers for signal routing. This segmentation distributes interconnect traffic across multiple dedicated pathways, reducing congestion and improving signal integrity.
3Adaptability or versatility
If heterogeneous technology integration is implemented, then design flexibility increases, but manufacturing complexity increases
Solution Approach 1:
The package substrate serves multiple functions simultaneously: it provides mechanical support for the stacked dies, acts as an interconnection platform with embedded traces and vias, provides thermal management through heat dissipation structures, and enables electrical connections to external circuit boards. This multi-functionality reduces the need for separate components and simplifies the overall manufacturing process.
Solution Approach 2:
The package substrate acts as an intermediary platform that interfaces between different heterogeneous dies and the external world. It provides standardized connection interfaces and routing that can accommodate various die types and technologies, simplifying the integration process by decoupling the complexity of heterogeneous interfacing from the manufacturing process.
Data Source
AI summary
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.