Double-Sided DRAM Cell Layout for Higher 3D Memory Density
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Solution Overview
Problem
The existing 1T-1C DRAM bit cell architecture has reached a fundamental limit due to elevated leakage and physical space constraints, hindering further scaling, and two-dimensional memory chips cannot significantly increase memory density without a change in memory array architecture, necessitating innovative approaches for higher density and bandwidth.
Innovation Solution
The implementation of a double-sided DRAM cell structure with a stacked transistor architecture, featuring a frontside and backside bit cell configuration, where each bit cell includes a stacked transistor structure with GAA channels and MIM capacitors, allowing for increased density through monolithic 3D integration within a single IC die, leveraging backside transistor interconnect technology and advanced CMOS circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 1T-1C DRAM bit cell architecture is used, then device simplicity and ease of manufacture are maintained, but memory density and communication bandwidth are limited due to physical space constraints and elevated leakage
Solution Approach 1:
The patent transitions from traditional 2D memory array architecture to a 3D stacked transistor structure where multiple channel regions are vertically stacked. This dimensional change allows multiple bit cells to occupy a smaller footprint area, effectively doubling or quadrupling memory density without proportionally increasing the planar area, thus resolving the contradiction between memory density and device complexity.
Solution Approach 2:
The patent implements nested capacitors where a first capacitor is positioned within or adjacent to the stacked transistor structure and a second capacitor is positioned on the opposite side, creating a compact nested arrangement. This nesting principle allows multiple capacitive elements to share the same spatial region, increasing storage capacity without linearly increasing device area.
2Quantity of substance
If 2D memory chip architecture is used, then manufacturing processes remain simple, but memory density cannot be significantly increased without fundamental architectural changes
Solution Approach 1:
The patent employs 3D stacking of transistor channels vertically, transforming the traditional 2D planar layout into a three-dimensional structure. This allows memory density to be doubled or quadrupled by utilizing the vertical dimension, while the manufacturing process builds upon existing CMOS fabrication techniques with minimal additional complexity.
Solution Approach 2:
The stacked transistor structure serves multiple functions simultaneously: it provides multiple channel regions for increased density, maintains compatibility with standard CMOS fabrication processes, and enables both high-density memory storage and continued ease of manufacture through established industrial processes.
3Quantity of substance
If stacked transistor structures are implemented, then transistor density is improved, but leakage increases and physical space constraints are exacerbated
Solution Approach 1:
The patent positions capacitors in nested configurations around and within the stacked transistor structure, with capacitors on both sides of the transistor stack. This compact nested arrangement increases effective storage density while maintaining tight integration that reduces parasitic effects and leakage paths compared to more spread-out configurations.
Data Source
AI summary
Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.