Double-Sided DRAM Cell Arrays With Stacked Transistors for Higher Density
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Solution Overview
Problem
The challenge is to enhance memory density and communication bandwidth in DRAM ICs while reducing costs, as existing technologies face limitations in scaling due to elevated leakage and physical space constraints in 1T-1C bit cells.
Innovation Solution
The implementation of double-sided DRAM cells with stacked transistor structures, where a frontside bit cell is stacked over a backside bit cell, each equipped with capacitors, allowing for a monolithic 3D array configuration within a single IC die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 1T-1C bit cell architecture is used, then memory density can be maintained at current levels, but further scaling is limited due to elevated leakage and physical space constraints
Solution Approach 1:
The patent transitions from traditional 2D memory array architecture to a 3D stacked transistor structure where multiple channel regions are vertically stacked. This dimensional change allows memory cells to be arranged in three dimensions rather than just two, effectively increasing storage density without proportionally increasing the footprint area on the substrate.
Solution Approach 2:
The patent implements nested structures where gate electrodes surround channel regions in a gate-all-around configuration, and multiple transistor channels are stacked vertically within a compact footprint. This nesting approach maximizes the use of available space by placing functional elements in three-dimensional space rather than just planar arrangement.
2Productivity
If stacked transistor structures are implemented, then transistor density improves for advanced logic circuits, but memory architecture requires fundamental change to leverage this
Solution Approach 1:
The patent creates a universal stacked transistor structure that can serve both logic circuit functions and memory storage functions. The same vertical stack architecture provides high-density transistors for logic while simultaneously enabling high-capacitance storage for memory, allowing one structure to fulfill multiple functional requirements.
Solution Approach 2:
The patent segments the memory array into multiple stacked transistor channels, where each channel can be independently controlled by its own gate electrode. This segmentation allows for fine-grained control of individual memory cells while maintaining high overall density, and enables selective activation of different memory regions.
3Quantity of substance
If gate-all-around stacked transistor structures are used, then transistor density increases, but capacitor integration space is reduced
Solution Approach 1:
The patent moves capacitor integration from a 2D planar arrangement to a 3D vertical arrangement. Capacitors are positioned above and below the stacked transistor channels, utilizing the vertical dimension for capacitor placement rather than requiring additional lateral space. This allows capacitor elements to be integrated within the same footprint as the transistor stack.
Solution Approach 2:
The patent merges the transistor and capacitor functions into a single integrated bit cell structure. The capacitor is physically combined with the stacked transistor channels in a shared footprint, where the same vertical space accommodates both the active transistor channels and the capacitor elements, reducing overall cell area.
Data Source
AI summary
Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.