Double-Sided Fan-Out Package Structure Without TSV Interconnects
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Solution Overview
Problem
Current 3D stacked bonding packaging processes for memory chips face challenges such as high costs, low packaging yields, and reduced data transmission rates due to reliance on TSV interconnection and wire bonding technologies, which are complex and costly, and result in long signal transmission delays and poor heat dissipation.
Innovation Solution
A double-sided stacked packaging scheme that eliminates the need for TSVs and wires and carrier plate lines, and instead uses a substrate with a substrate with a double-sided fan-out package structure comprising through-vias and redistribution layers comprising through-vias and redistribution layers comprising through-vias and redistribution layers comprising through-vias and through-redistribution via and through-via and through-vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV technology is used for chip interconnection, then interconnect density is improved, but process complexity and cost increase significantly
Solution Approach 1:
The patent extracts and eliminates the TSV fabrication process from the packaging flow. Instead of forming vertical silicon vias through the substrate, the invention uses a planar redistribution layer approach where conductive traces are formed on the substrate surface to interconnect chips laterally, thereby removing the complex TSV formation steps including silicon via drilling, copper pillar deposition, and NCF/NCP material processing
Solution Approach 2:
The patent replaces expensive TSV materials (NCF, NCP, copper pillars) with a simpler, more cost-effective redistribution layer structure using standard PCB trace technologies. The substrate itself serves as the interconnection medium through printed circuit board-style traces, eliminating the need for specialized TSV materials and reducing overall packaging costs
2Ease of manufacture
If wire bonding is used for chip interconnection, then packaging process is simplified, but signal transmission delay increases and bandwidth is limited
Solution Approach 1:
The patent transitions from three-dimensional wire bonding (vertical connections through carrier plates) to two-dimensional planar trace routing on the substrate surface. This dimensional change allows direct lateral connection between chip pads and substrate interconnects, eliminating the need for wire bonds and carrier plates, and reducing signal path length while maintaining manufacturing simplicity
3Reliability
If TSV and wire bonding technologies are used, then chip stacking is achieved, but packaging cost increases and packaging yield decreases
Solution Approach 1:
The patent merges the substrate function with the interconnection function by integrating redistribution traces directly into the substrate structure. This consolidation eliminates separate wire bonding and TSV fabrication steps, reducing the number of process stages and potential failure points, thereby improving packaging yield while maintaining chip stacking capability
Solution Approach 2:
The substrate is designed to perform multiple functions simultaneously: mechanical support for stacked chips, electrical interconnection through redistribution traces, and signal routing to external pins. This multi-functionality eliminates the need for separate carrier plates and wire bonds, simplifying the overall packaging process and improving yield
4Reliability
If TSV technology is used, then vertical interconnection is achieved, but material cost and equipment cost increase
Solution Approach 1:
The patent uses standard PCB trace copying techniques to create interconnection patterns on the substrate, replacing the need for expensive TSV fabrication. The redistribution layer traces are formed using conventional photolithography and copper deposition processes similar to PCB manufacturing, which are far less costly than TSV formation requiring specialized equipment and materials
Data Source
AI summary
Disclosed are double-sided stacked fan-out package structure and fabrication method thereof, the package structure comprising a substrate with vias; chips stacked in layers; an encapsulation material layer; redistribution layers disposed on the encapsulation material layer; a first conductive structure through which the chips on a first surface are electrically connected to the redistribution layer; and a second conductive structure extending through the thickness of the substrate. Some sections of the second conductive structure are disposed in some vias in the substrate, and the redistribution layers on the first surface and a second surface of the substrate are electrically connected via the second conductive structure. With the second conductive structure electrically connecting the chips on both surfaces of the substrate, it avoids forming through silicon vias in the chips, reducing packaging costs and improving packaging yield; and meanwhile avoids chip interconnections through carrier plates and wires, improving transmission efficiency.