Double-Sided IC Structures for Back-Side Transistor Access
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Solution Overview
Problem
Current 3D integration techniques for integrated circuits face challenges in reducing structural dimensions and increasing device density, particularly due to limitations in through-substrate via technology and difficulties in fabricating terminals for vertically-oriented device architectures.
Innovation Solution
The implementation of double-sided processing methods, including back-side reveal techniques, which allow for the removal of substrate material to expose device layers at the transistor level, enabling more intimate back-side processing and reducing the need for microns-deep conductive vias, and the use of permanent bonds for mechanical rigidity and precise thickness control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If through-substrate via technology is used to vertically interconnect chip stacks, then electrical connections can be established through the substrate, but the via diameters are limited to micron-scale and the substrate thickness cannot be significantly reduced
Solution Approach 1:
The patent transitions from lateral via formation to vertical finFET architecture where the channel extends in the z-dimension. This dimensional change allows electrical connections to be made at the back-side of the substrate through exposed fin structures, eliminating the need for microns-deep TSVs and enabling significant substrate thickness reduction.
Solution Approach 2:
The finFET structures are formed with extended vertical channels before substrate thinning. This preliminary formation of vertically-oriented devices allows subsequent back-side processing to access the channel regions directly, enabling precise nanometer-level connections without requiring deep through-substrate vias.
2Ease of manufacture
If laterally-oriented transistors are used, then terminal fabrication is straightforward, but device density and z-height reduction are limited
Solution Approach 1:
The patent adopts vertically-oriented finFET architecture where the transistor channel extends perpendicular to the substrate surface. This vertical orientation increases device density by utilizing the z-dimension for channel length, while back-side processing provides straightforward access to source/drain terminals similar to lateral devices.
Solution Approach 2:
Instead of accessing transistor terminals from the front-side as in conventional lateral devices, the patent inverts the approach by forming vertically-oriented fins and accessing terminals from the back-side of the substrate. This inversion enables both high device density and ease of terminal fabrication.
3Productivity
If chip stacking with TSV technology is implemented, then 3D integration is achieved, but the final z-height is hundreds of microns thicker than the actual device layers
Solution Approach 1:
The patent extracts and removes the bulk inactive substrate material after finFET formation, retaining only the necessary thin substrate portion with exposed vertical fin structures. This extraction eliminates the hundreds of microns of overhead thickness associated with conventional TSV stacking, reducing the final chip stack z-height to be much closer to the actual device layer thickness.
4Strength
If substrate material is retained to provide mechanical support, then structural integrity is maintained, but device thickness and density are compromised
Solution Approach 1:
Vertically-oriented finFET structures are formed preliminary to substrate thinning. These robust vertical structures provide inherent mechanical strength and structural integrity, enabling subsequent removal of bulk substrate material without compromising the device's structural stability, thus reducing device thickness while maintaining strength.
Data Source
AI summary
Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.