Double-Sided IC Chip Wafer Bonding for Thermal Isolation
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Solution Overview
Problem
The challenge in fabricating integrated circuit chips is to enhance the performance of different devices on a single chip without adverse thermal effects, which is difficult and costly due to the need to optimize fabrication processes for various device types simultaneously.
Innovation Solution
The method involves fabricating devices on separate silicon-on-insulator wafers with buried oxide layers, bonding these wafers to create a double-sided integrated circuit chip, and forming conductive contacts and wiring levels to interconnect devices, allowing for independent optimization of device parameters like crystal orientation and thermal budgets without affecting each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fabrication processes are optimized for different device types simultaneously on a single chip, then device performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the integrated circuit chip into two separate wafers, each dedicated to specific device types. First wafer contains first devices (e.g., NFETs) and second wafer contains second devices (e.g., PFETs). Each wafer can be fabricated with optimized processes tailored to its specific device type, avoiding the complexity of simultaneously optimizing multiple device types on a single chip. The wafers are subsequently bonded together to form the complete integrated circuit.
2Reliability
If thermal cycles are adjusted to enhance performance of one set of devices, then those devices improve, but other devices on the same chip are adversely affected
Solution Approach 1:
By segmenting the chip into two separate wafers, each wafer can undergo thermal cycles optimized for its specific device type without affecting other devices. For example, first wafer can be subjected to thermal cycles appropriate for NFETs while second wafer undergoes thermal cycles appropriate for PFETs, eliminating thermal interference between device types.
3Manufacturing precision
If fabrication process is centered around one device specification, then that device type performs well, but other device types cannot be simultaneously optimized
Solution Approach 1:
The patent enables each wafer to be fabricated with process parameters specifically centered around the requirements of its designated device type. First wafer fabrication can be optimized for first devices while second wafer fabrication is optimized for second devices, achieving high manufacturing precision for each device type simultaneously through spatial separation.
Solution Approach 2:
The patent transitions from a single-plane fabrication approach to a multi-layer stacked architecture. By utilizing the vertical dimension through wafer bonding, the system achieves multi-device optimization without compromising manufacturing precision for any single device type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables cost-effective enhancement of device performance by allowing independent optimization of different types of devices on a single chip, reducing thermal interference and improving device characteristics such as mobility and threshold voltage.
Implementation Method 1
bonding the surface of the first buried oxide layer to the surface of the second buried oxide layer
Data Source
AI summary
Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.