Double-Sided IC Die Layout for High-Density TSV Interconnects
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Solution Overview
Problem
Existing semiconductor technologies face challenges in increasing integration density and improving signal transmission efficiency between components, particularly in 3D integrated circuits, while also requiring efficient heat dissipation and supporting diverse semiconductor materials like GaAs, GaN, and SiC.
Innovation Solution
The integration of a double-sided integrated circuit die with symmetrical layouts on both sides of a substrate, utilizing TSVs for vertical interconnects, and a package structure that allows for high-bandwidth memory implementation, enabling efficient signal transmission and heat dissipation across both sides of the die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D package with edge wiring is used to increase interconnect density, then connectivity between chips is improved, but the package length and width increase
Solution Approach 1:
The patent transitions from 2D edge wiring to 3D vertical interconnection through TSVs. By forming vertical connections through the chip body, the interconnect density increases in the vertical dimension while maintaining a compact footprint, thus resolving the contradiction between interconnect density and package area.
Solution Approach 2:
Instead of wiring chips along their edges (horizontal connection), the patent inverts the approach by forming vertical connections through the chip body using TSVs. This inversion of the connection direction enables higher interconnect density without increasing package area.
2Reliability
If an interposer layer is added between stacked chips to improve connectivity, then signal transmission is enhanced, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the interposer layer from the 3D package structure. By directly bonding chips together with TSV-based vertical interconnections, the complex interposer layer is removed while maintaining signal transmission quality, thus reducing device complexity.
3Productivity
If integration density is increased through 3D stacking to improve productivity, then component density is enhanced, but heat dissipation becomes more difficult
Solution Approach 1:
The patent utilizes the vertical dimension for heat dissipation by implementing heat sinks and thermal management structures on the top and bottom surfaces of the stacked chips. This three-dimensional thermal management approach enables effective heat dissipation while maintaining high integration density through vertical stacking.
Data Source
AI summary
According to one aspect of the disclosure, there is provided an integrated circuit die includes: a substrate; a head structure including a first device layer in a head side of the substrate, a first wiring layer on the first device layer, and a first passivation layer on the first wiring layer, and a tail structure including a second device layer in a tail side of the substrate opposite to the head side, a second wiring layer on the second device layer, and a second passivation layer on the second wiring layer, wherein the tail structure is horizontally symmetrical to the head structure at least partially in view of an integrated circuit layout perspective.