Double-Sided IC Die Layout With TSVs for Dense 3D Packaging
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Solution Overview
Problem
Existing semiconductor technologies face challenges in increasing integration density and improving signal transmission speed and thermal management in integrated circuits, particularly in 3D packages and ICs, while efficiently utilizing diverse semiconductor materials.
Innovation Solution
The integration of semiconductor ICs on both sides of a substrate with vertical interconnects (TSVs) and heat dissipation members, allowing for high-density integration and fast signal transmission between components, including heterogeneous processes, and effective heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are stacked vertically in a 3D package with edge wiring, then interconnect density is increased, but package length and width increase
Solution Approach 1:
The patent transitions from 2D edge wiring to 3D vertical interconnection through TSVs. By forming through-silicon vias that penetrate the substrate vertically, the interconnect architecture moves from horizontal routing at chip edges to vertical routing through the chip body, enabling higher density without increasing package footprint.
Solution Approach 2:
The patent implements nested interconnection structures where TSVs are embedded within the substrate, and multiple interconnect layers are stacked vertically. The TSVs are formed by etching holes through the substrate and filling them with conductive material, creating nested conductive pathways that integrate multiple connection functions within the same vertical space.
2Area of stationary object
If TSV technology is used to replace edge wiring, then package area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the interconnection formation process into distinct segments: substrate preparation, TSV hole etching, insulation layer deposition, conductive filling, and planarization. This segmentation allows each manufacturing step to be optimized independently and enables parallel processing of multiple TSVs across the substrate, reducing overall manufacturing complexity despite the advanced process requirements.
Solution Approach 2:
The patent performs preliminary actions by forming TSV holes and depositing insulation layers before final chip assembly and stacking. The TSV structures are pre-formed within the substrate during wafer fabrication, allowing subsequent chip stacking to proceed without additional complex alignment steps, thereby reducing overall manufacturing complexity.
3Quantity of substance
If integration density is increased through 3D stacking, then functionality per footprint is improved, but heat dissipation becomes more difficult
Solution Approach 1:
The patent introduces thermal interface materials and heat spreader layers as intermediary structures between stacked chips and the heat sink. These intermediary layers facilitate efficient thermal coupling while accommodating dimensional variations, enabling effective heat dissipation from the high-density 3D stacked configuration without compromising integration density.
Data Source
AI summary
According to one aspect of the disclosure, there is provided an integrated circuit die includes: a substrate including a front side and a back side opposite to the front side; a front structure including a first element layer on the front side of the substrate and a first wiring layer on the first element layer; and a back structure including a second element layer on the back side of the substrate and a second wiring layer on the second element layer.