Double-Sided IPD Package Shielding for EMI and RFI Control
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Solution Overview
Problem
Semiconductor devices face challenges in managing electromagnetic interference (EMI), radio frequency interference (RFI), and inter-device interference such as capacitive, inductive, or conductive coupling, which can interfere with their operation, especially in high-speed digital circuits, while simultaneously achieving higher performance, higher integration, and miniaturization.
Innovation Solution
The implementation of a semiconductor device with a double-sided integrated passive device (IPD) and a shielding frame to mitigate interference, using conductive materials like Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials, and optionally a heat sink for thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shielding is added to manage EMI and RFI, then interference protection is improved, but device complexity increases
Solution Approach 1:
The patent combines the shielding frame with the substrate by forming conductive traces on the substrate that electrically connect to the shielding frame. This integration merges two previously separate components (shielding and substrate) into a unified structure, reducing overall device complexity while maintaining effective EMI and RFI protection.
2Productivity
If double-sided IPD integration is implemented, then integration density is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent divides the IPD integration into two separate sides (first side and second side) of the substrate, with each side having its own set of conductive traces and connections. This segmentation allows for independent fabrication and testing of each side, simplifying the manufacturing process while achieving high integration density through double-sided mounting.
3Volume of moving object
If miniaturization is pursued, then device size is reduced, but heat dissipation becomes more difficult
Solution Approach 1:
The patent utilizes the third dimension by implementing double-sided IPD integration, where passive devices are mounted on both the top and bottom surfaces of the substrate. This vertical stacking approach reduces the horizontal footprint (miniaturization) while distributing heat generation across multiple surfaces, improving heat dissipation through enhanced surface area for thermal management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces EMI, RFI, and inter-device interference, enhancing the performance and integration of semiconductor devices while maintaining miniaturization, thus improving operational reliability and reducing manufacturing costs.
Implementation Method 1
The implementation of a semiconductor device with a double-sided integrated passive device (IPD) and a shielding frame to mitigate interference
Implementation Method 2
using conductive materials like Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials
Implementation Method 3
and optionally a heat sink for thermal management
Data Source
AI summary
A semiconductor device has a semiconductor die, substrate, and plurality of first conductive pillars formed over the semiconductor die or substrate. Alternatively, the first conductive pillars formed over the semiconductor die and substrate. An electrical component is disposed over the semiconductor die. The electrical component can be a double-sided IPD. The semiconductor die and electrical component are disposed over the substrate. A shielding frame is disposed over the semiconductor die. A plurality of second conductive pillars is formed over a first surface of the electrical component. A plurality of third conductive pillars is formed over a second surface of the electrical component opposite the first surface of the electrical component. A bump cap can be formed over a distal end of the conductive pillars. The substrate has a cavity and the electrical component is disposed within the cavity. An underfill material is deposited between the semiconductor die and substrate.