Double-Sided Local Interconnect for High-Density PoP Packaging

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density and communication bandwidth between integrated circuit dies while maintaining low contact resistance and high reliability, particularly in Package-on-Package (PoP) technology.

Innovation Solution

The implementation of a double-sided local interconnect component embedded in a redistribution structure, which provides electrical connections between integrated circuit dies without the need for an interposer, thereby reducing warpage mismatch and enhancing signal and power integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If Package-on-Package (PoP) technology is used to increase integration density, then component density and functionality are enhanced, but warpage mismatch and contact resistance increase

Engineering Contradiction:
Improveintegration densityVSAvoidwarpage mismatch
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces a redistribution structure as an intermediary component between the first and second semiconductor packages. This redistribution structure includes conductive vias and metallization layers that facilitate electrical connection while accommodating dimensional mismatches, thereby reducing warpage issues and contact resistance in PoP configurations

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent divides the interconnection system into separate functional components: the first semiconductor package, the redistribution structure, and the second semiconductor package. This segmentation allows each component to be optimized independently, with the redistribution structure specifically designed to handle warpage and alignment tolerances

Inventive Principle:
Principle #1Segmentation

2Reliability

If conventional interposer structures are used to connect integrated circuit dies, then electrical connections are established, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidinterposer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The redistribution structure serves multiple functions simultaneously: it provides electrical interconnection between dies, enables signal routing, accommodates thermal expansion differences, and provides mechanical support. This multi-functionality eliminates the need for separate interposer components, reducing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the interconnection function with the existing redistribution structure that is already part of the semiconductor package fabrication process. By integrating the interconnect functionality into the redistribution structure rather than adding a separate interposer, the patent simplifies the overall device architecture

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If minimum feature size is reduced to increase integration density, then more components are integrated into a given area, but manufacturing precision requirements increase

Engineering Contradiction:
Improveintegration densityVSAvoidminimum feature size
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent addresses the limitations of scaling in the lateral dimension by utilizing the vertical dimension through stacked Package-on-Package configuration. The redistribution structure enables three-dimensional interconnection, allowing integration density to increase without proportionally reducing minimum feature size in the planar direction

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12334446B2Semiconductor package and method
Publication Date: 2025.06.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12334446B2 patent drawing
  • US12334446B2 patent drawing
  • US12334446B2 patent drawing

AI summary

A semiconductor structure includes a first redistribution structure, a first local interconnect component disposed on the first redistribution structure, and a first interconnect structure over a second side of the first local interconnect component. The first local interconnect component includes a first plurality of redistribution layers. The first plurality of redistribution layers includes a first plurality of conductive features on a first side of the first local interconnect component. Each of the first plurality of conductive features are coupled to respective conductive features of the first redistribution structure. The first interconnect structure includes a second plurality of conductive features and a third plurality of conductive features. The second plurality of conductive features are electrically coupled to the third plurality of conductive features through the first local interconnect component.