Double-Sided Multichip Packaging With Direct Die-to-Die Coupling
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Solution Overview
Problem
Existing multichip packaging technologies face challenges in efficiently integrating semiconductor devices with varying footprints and thicknesses, and in forming direct electrical connections between them, leading to inefficiencies in space utilization and performance.
Innovation Solution
A method for fabricating multichip packages that allows for direct bonding and electrical interconnections between semiconductor devices, using polymeric materials to encapsulate and embed devices in multiple layers, with redistribution layers and internal interconnects to facilitate connections across different surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple devices are assembled within one package, then space utilization is improved, but device complexity increases
Solution Approach 1:
The patent implements vertical stacking of multiple semiconductor devices within a single package, with devices nested in different layers (first device in lower layer, second device in upper layer). This nesting approach maximizes space utilization by utilizing the third dimension (vertical space) rather than expanding horizontally, while the shared substrate and integrated interconnect structure help manage the complexity of multi-device integration.
Solution Approach 2:
The patent transitions from traditional horizontal/2D device arrangement to vertical/3D stacking configuration. Devices are positioned at different heights (lower layer and upper layer) with direct die-to-die coupling through vertical interconnects, enabling compact integration while maintaining electrical connectivity through the third dimension.
2Reliability
If direct electrical connections are formed between devices, then performance is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent incorporates through-substrate vias and interconnect structures during the substrate fabrication stage, before devices are mounted. This preliminary formation of electrical pathways simplifies subsequent device integration, as the interconnect infrastructure is already in place to receive and connect to the stacked devices.
Solution Approach 2:
The patent combines multiple functions into integrated structures: the substrate serves as both mechanical support and electrical interconnection medium, while through-substrate vias simultaneously provide mechanical alignment features and electrical pathways. This merging of functions reduces the number of separate manufacturing steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of semiconductor devices with diverse sizes and thicknesses in a single package, enhancing space efficiency and performance by allowing direct bonding and electrical connections, thus improving device performance characteristics such as clock speeds and power dissipation.
Implementation Method 1
The first surface of the second electronic component physically contacts and is bonded to the first surface of the first electronic component
Implementation Method 2
A volume of molding material encapsulates the first electronic component and the second electronic component
Implementation Method 3
An internal interconnect passes through the volume of molding material and the aperture in the first electronic component. The internal interconnect electrically couples an electrically conductive interconnect in the first redistribution layer to an electrical contact pad belonging to the second electronic component
Implementation Method 4
An upper set of redistribution layers is formed from layers of electrically-insulating material that surround a first set of electrically conductive interconnects
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
A multi-chip package includes two electronic components bonded to each other via features on corresponding faces of the components that are directly opposite each other. The components are encapsulated in a volume of molding material that can include upper and lower sets of redistribution layers disposed on upper and lower surfaces of the volume of molding material that include electrical interconnects. The package includes one or more internal interconnects that pass through an aperture in the first electronic component to electrically couple an electrical contact on a surface of the package to the second electronic component.