Double-Sided Semiconductor Package With Overlapping Power Terminals
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving sufficient cooling, low impedance, and low leakage inductances, particularly in high-current electrical circuits such as those used in electric vehicle drives.
Innovation Solution
A semiconductor package with a double-sided cooling structure is designed, featuring an upper electrically conductive element, a lower carrier substrate with overlapping power terminals, and a method for producing such a package that includes applying electrically conductive spacers and encapsulating the components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional single-sided cooling structure is used, then device complexity is low, but cooling efficiency is insufficient
Solution Approach 1:
The cooling structure is segmented into two independent cooling paths: an upper cooling plate contacting the upper surface of the semiconductor chip, and a lower cooling plate contacting the lower surface of the chip. This segmentation allows heat to be dissipated from both sides of the chip simultaneously, doubling the effective cooling area and improving cooling efficiency without requiring a completely new device architecture.
Solution Approach 2:
The invention transitions from single-sided (one-dimensional) cooling to double-sided (two-dimensional) cooling by adding cooling capability in the vertical dimension. The lower cooling plate is introduced beneath the chip, creating a symmetric cooling arrangement that utilizes both upper and lower surfaces of the semiconductor chip for heat dissipation.
2Reliability
If power terminals are arranged separately without overlap, then manufacturing is simpler, but inductance is higher
Solution Approach 1:
The invention merges the upper and lower power terminals in the vertical direction to create overlapping regions. The upper power terminal extends downward and the lower power terminal extends upward, causing them to overlap in space. This merging of terminals reduces the current loop area and minimizes parasitic inductance, improving electrical performance while maintaining a manageable manufacturing process.
3Power
If impedance is reduced for high-current circuits, then performance improves, but leakage inductance becomes more critical
Solution Approach 1:
The overlapping arrangement of upper and lower power terminals creates equipotential regions that minimize potential differences and reduce leakage inductance. By positioning the terminals to overlap vertically, the invention ensures that current returns follow the shortest possible path, minimizing the area enclosed by current loops and thereby reducing parasitic inductance effects that would otherwise limit high-current performance.
Data Source
AI summary
A semiconductor package includes an encapsulant body; a first electrically conductive element having an outwardly exposed metal surface; a first carrier substrate having a first electrically conductive layer, a second electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the first electrically conductive element and the first electrically conductive layer; a power semiconductor chip between the first electrically conductive element and the first electrically conductive layer; and a second electrically conductive spacer between the first electrically conductive element and the power semiconductor chip, a first carrier region of the first electrically conductive layer is connected to a first power terminal, a second carrier region of the first electrically conductive layer is alongside the first carrier region and is connected to a second power terminal, a first region of the first electrically conductive element is connected to a third power terminal.