Double-Sided RDL Package Substrate for Signal Path Reduction
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Solution Overview
Problem
Existing package substrates with long signal communication paths between chips suffer from weakened signal strength due to longer circuitry lengths, necessitating a shorter communication path for efficient signal transmission.
Innovation Solution
A package substrate design featuring a middle redistribution layer sandwiched by top and bottom redistribution layers, with varying metal pad densities and line widths, and a flexible circuit board for efficient electrical coupling, allowing for shorter circuitry paths between neighboring chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are mounted on opposite sides of the package substrate with existing interposer configuration, then system integration is achieved, but signal communication path becomes long causing signal weakening
Solution Approach 1:
The patent transitions from a single-sided chip mounting configuration to a double-sided chip mounting configuration on the package substrate. By utilizing both the top and bottom surfaces of the substrate, neighboring chips on opposite sides can communicate through the substrate thickness dimension rather than traveling across the substrate surface, significantly shortening the signal path length and reducing signal attenuation.
Solution Approach 2:
The package substrate is divided into multiple functional layers including a first redistribution layer (RDL) on the top surface, a second RDL on the bottom surface, and an intermediate layer containing vias. This segmentation allows independent optimization of each layer for signal routing, with the intermediate layer providing direct vertical coupling between the two RDLs to minimize path length.
2Length of moving object
If multiple redistribution layers with different line widths are used to enable double sided chip mounting, then shorter communication paths are achieved, but manufacturing complexity increases
Solution Approach 1:
The patent employs different line widths in different regions of the redistribution layers. Specifically, the first RDL includes first metal lines with a first line width for certain connections, while the second RDL includes second metal lines with a second line width for corresponding connections on the opposite side. This local variation in line width allows optimization of signal characteristics for different routing requirements while maintaining overall design simplicity.
Solution Approach 2:
The patent varies the electrical parameters of the redistribution layers by using different metal line widths in different layers. The first line width and second line width are specifically selected to achieve desired signal impedance and current carrying capacity for their respective routing functions, allowing parameter optimization without increasing structural complexity.
Data Source
AI summary
A package substrate has a sandwiched redistribution layers is disclosed. A middle redistribution layer functions as a core redistribution layer sandwiched by a top redistribution layer and a bottom redistribution layer. A top surface of the top redistribution layer is made adaptive for at least one chip to mount, and a bottom surface of the bottom redistribution layer is made adaptive for at least one chip to mount. A line width of each circuit of the middle redistribution layer is wider than a circuit of either the top redistribution layer or the bottom redistribution layer.