Double-Sided Semiconductor Structure for High-Density Integration
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Solution Overview
Problem
Conventional CMOS integrated circuits with devices of P and N types on the same substrate face challenges in production density, contact connection, and signal propagation delays when trying to house multiple devices in a single package, as they require separate process steps and materials, increasing costs and complexity.
Innovation Solution
A double-sided semiconductor structure is developed, where a substrate with semiconductor layers of different conductivity types on opposite sides allows for the formation of active electronic devices like MOSFETs and Schottky diodes on both sides, sharing a common drain region and guard rings, enabling efficient electrical contact and reduced parasitic inductances without external connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple devices of different types are formed on the same substrate using separate process steps, then device functionality is achieved, but production density decreases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar device arrangement to three-dimensional vertical arrangement by forming devices on both sides of the substrate. This dimensional change allows doubling of device density without increasing lateral footprint, directly resolving the contradiction between production density and process complexity.
Solution Approach 2:
The substrate is divided into two functional sides, each hosting independent semiconductor layers and devices. This segmentation allows parallel processing of opposite-side devices and eliminates the need for complex sequential masking operations, thereby increasing production density while reducing process complexity.
2Loss of time
If devices are housed in a single package to reduce propagation delay, then signal propagation delay decreases, but contact connection complexity increases
Solution Approach 1:
The patent merges the contact formation processes for opposite-side devices by routing all contacts through a single set of vias formed in the substrate. This consolidation reduces the number of separate connection steps required, thereby decreasing contact connection complexity while maintaining single-package integration for reduced signal delay.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it acts as a mechanical support structure, an electrical interconnection medium, and a platform for housing multiple device types. This multi-functionality reduces the need for additional connection structures, simplifying contact complexity while enabling compact single-package integration.
3Reliability
If separate wafers are used for different device types to optimize performance, then device performance is optimized, but production costs increase
Solution Approach 1:
The patent accommodates different device types on opposite sides of the same substrate, effectively using the third dimension (substrate thickness) to separate device types. This approach maintains the performance optimization benefits of separate device fabrication while eliminating the need for multiple wafers, thereby reducing production costs through wafer-level integration.
Solution Approach 2:
The substrate is segmented into two independent processing zones (opposite sides), each optimized for specific device types. This segmentation allows different semiconductor layers and process parameters to be applied to each side, maintaining device performance optimization while reducing overall production costs by processing both device types in a single wafer fabrication cycle.
Data Source
AI summary
A semiconductor structure including a substrate of semiconductor material of a first type of conductivity; a first semiconductor layer set in direct electrical contact with the substrate on a first side of the substrate; a second semiconductor layer set in direct electrical contact with the substrate on a second side of the substrate; a first active electronic device formed in the first semiconductor layer; and a second active electronic device formed in the second semiconductor layer.