Double-Sided Staircase Structures for 3D Memory Routing
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Solution Overview
Problem
Conventional 3D memory devices face challenges in increasing storage capacity due to constrained interconnect routing and high interconnect density, as conventional staircase structures allow word line fan-out only on one side of the substrate, limiting routing flexibility and process window.
Innovation Solution
The development of staircase structures for 3D memory devices that enable double-sided routing, allowing interconnect routing on both sides of the substrate, thereby increasing routing flexibility and reducing interconnect density, and potentially eliminating the need for high-aspect-ratio interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional staircase structures are used for interconnect routing, then the structure is simple to fabricate, but routing flexibility is limited and interconnect density is high
Solution Approach 1:
The patent transitions from conventional single-sided staircase structures to double-sided staircase structures that extend interconnect routing to both front and back sides of the substrate. This dimensional expansion allows word lines to be routed out from both edges of the memory stack, effectively doubling the routing capacity and flexibility without requiring higher aspect ratios or more complex single-sided interconnect designs
2Productivity
If single-sided word line fan-out is used, then fabrication process is simpler, but routing capacity is constrained
Solution Approach 1:
The interconnect routing is segmented into two independent pathways: front-side routing and back-side routing. Each side has its own staircase structure that can independently route word lines to opposite edges of the substrate. This segmentation doubles the effective routing capacity while keeping each individual routing path relatively simple, avoiding the need for highly complex single-sided routing solutions
3Productivity
If high-aspect-ratio interconnect structures are used, then storage capacity increases, but device yield decreases due to manufacturing difficulty
Solution Approach 1:
Instead of increasing the height or aspect ratio of single-sided interconnect structures to achieve higher storage capacity, the patent distributes the routing function across both sides of the substrate. This approach maintains moderate aspect ratios for all interconnect structures while achieving enhanced capacity through doubled routing pathways, thereby improving manufacturability and device yield
Data Source
AI summary
Embodiments of methods of forming staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a first dielectric layer is formed on a substrate, and a first photoresist layer is formed on the first dielectric layer. A recess is patterned through the first dielectric layer to the substrate by cycles of trim-etch the first dielectric layer. Dielectric/sacrificial layer pairs are formed on the first dielectric layer and filling in the recess. A second photoresist layer is formed on the dielectric/sacrificial layer pairs. The dielectric/sacrificial layer pairs are patterned by cycles of trim-etch the dielectric/sacrificial layer pairs. A second dielectric layer is formed on the first dielectric layer and covering the patterned dielectric/sacrificial layer pairs. A memory stack including conductor/dielectric layer pairs is formed by replacing, with conductor layers, the sacrificial layers in the patterned dielectric/sacrificial layer pairs and the dielectric/sacrificial layer pairs in the recess.