Double-Sided Interconnect Layout for Stacked and Planar Transistors
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Solution Overview
Problem
The integration of stacked and non-stacked transistors on a semiconductor wafer poses challenges in achieving efficient frontside and backside interconnects without increasing wafer area, while maintaining high performance and density.
Innovation Solution
A semiconductor structure with both stacked and non-stacked transistors, featuring multilayered frontside interconnects and backside metal levels, allows for electrical connections between transistors and other devices, utilizing frontside and backside interconnects to provide power without occupying additional wafer space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked transistors are integrated with non-stacked transistors on the same wafer, then device density is increased, but interconnect complexity increases
Solution Approach 1:
The patent utilizes the backside of the wafer as an additional dimension for interconnect routing. By forming backside interconnect structures that extend from the rear surface of the substrate to contact regions of both stacked and non-stacked transistors, the design offloads routing complexity from the crowded frontside to the underutilized backside, thereby increasing device density without proportionally increasing frontside interconnect complexity
Solution Approach 2:
The interconnect system is segmented into frontside and backside components. Frontside interconnects handle local connections while backside interconnects handle power delivery and global routing. This segmentation allows each layer to be optimized independently, reducing the overall complexity of integrating stacked and non-stacked transistors
2Use of energy by moving object
If frontside and backside interconnects are provided for both stacked and non-stacked transistors, then power delivery efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The backside interconnect structure serves multiple functions simultaneously: it provides power delivery to both stacked and non-stacked transistors, acts as a ground reference, and enables electrical isolation between different device regions. This multi-functionality improves power delivery efficiency without proportionally increasing manufacturing complexity, as a single structural element accomplishes multiple electrical functions
Solution Approach 2:
The backside interconnect system automatically provides power and reference potentials to devices without requiring additional frontside routing. The structure self-organizes to deliver power efficiently by utilizing the substrate thickness and backside access points, reducing the burden on frontside interconnect design and simplifying the overall manufacturing process
3Area of stationary object
If stacked transistors are used to increase device density, then wafer area is reduced, but interconnect routing difficulty increases
Solution Approach 1:
By utilizing the vertical dimension (wafer thickness) and the backside surface, the patent creates additional routing space for interconnects. Backside interconnect structures can be routed independently of frontside device layout, allowing complex connections to be made without increasing foot print area, as routing occurs in the unused backside dimension
Solution Approach 2:
The backside substrate acts as an intermediary medium that facilitates interconnect routing between stacked and non-stacked transistors. Rather than requiring direct frontside routing between densely packed devices, signals and power can be delivered through the backside substrate, which serves as a mediating layer that simplifies the routing topology
Data Source
AI summary
A semiconductor structure is provided that includes a stacked transistor including at least one transistor stacked over another transistor and a non-stacked transistor integrated on a same wafer. Both the stacked transistor and the non-stacked transistor include frontside and backside interconnects.