Double-Sided Vertical Semiconductor Device Thinned Substrate
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Solution Overview
Problem
Semiconductor power devices, particularly VDMOS structures, face limitations due to high junction capacitance, poor thermal performance, and the inability to independently contact source and channel regions, leading to inefficiencies in high-power applications.
Innovation Solution
The development of vertical power devices with minimized drain region dimensions, thin semiconductor substrates, and trench isolation techniques to reduce parasitic capacitance and thermal resistance, allowing independent biasing of source and body regions, and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the drain region thickness is increased to reduce junction capacitance, then the switching speed improves, but the breakdown voltage decreases
Solution Approach 1:
The drain region is segmented into multiple regions with different doping concentrations and thicknesses. The first drain region has a first doping concentration and thickness, while the second drain region has a second doping concentration and thickness, creating a graded structure that optimizes both capacitance and breakdown voltage characteristics
Solution Approach 2:
Different regions of the drain are given different local properties through varying doping concentrations. The first drain region and second drain region have distinct doping profiles, allowing each region to contribute differently to the overall device performance - one region optimizes for capacitance while the other optimizes for breakdown voltage
2Temperature
If the semiconductor substrate thickness is reduced to improve thermal dissipation, then the thermal resistance decreases, but the mechanical strength and handling reliability deteriorate
Solution Approach 1:
The semiconductor substrate is segmented into a first substrate portion and a second substrate portion with different thicknesses. The first substrate portion has a greater thickness than the second substrate portion, allowing the device to have excellent thermal dissipation through the thinner second portion while maintaining mechanical strength through the thicker first portion
Solution Approach 2:
Different portions of the substrate are given different local thickness properties to optimize for different functions. The first substrate portion maintains mechanical integrity, while the second substrate portion provides thermal dissipation pathways, creating a functionally optimized structure
3Power
If the channel width is increased to handle larger currents, then the current carrying capacity improves, but the junction capacitance increases
Solution Approach 1:
The channel is segmented into a first channel region and a second channel region with different widths. The first channel region has a first width and the second channel region has a second width, allowing the device to achieve high current carrying capacity through the wider first region while minimizing capacitance through the narrower second region
Solution Approach 2:
Different channel regions are given different local width properties to optimize for different electrical characteristics. The first channel region provides high current capacity, while the second channel region reduces parasitic capacitance, creating a balanced performance structure
Data Source
AI summary
A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.