Double-Sided Wafer Wiring With Through-Vias for Low-Delay Memory Stacking
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Solution Overview
Problem
The demand for further size reduction of semiconductor apparatuses persists despite existing size reduction technologies, and there is a need to increase semiconductor mounting per unit volume while minimizing signal delay.
Innovation Solution
A hybrid semiconductor apparatus utilizing both surfaces of a semiconductor layer with a first and second wire structure, along with a through via for electrical connection, where the first semiconductor element layer operates as a cache memory or logic circuit and the second semiconductor element layer operates as a main memory, allowing for reduced thickness and size by integrating functions on both surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor functions are integrated into a single chip (SOP) or packaged together (SIP), then the number of semiconductor mounting per unit volume increases, but the overall size of the semiconductor apparatus still cannot be reduced sufficiently
Solution Approach 1:
The patent utilizes both the front surface and back surface of the semiconductor substrate, transitioning from single-sided to double-sided utilization. The first semiconductor element layer is formed on the front surface while the second semiconductor element layer is formed on the back surface, effectively using the third dimension (depth/thickness) to increase functional density without increasing lateral footprint.
Solution Approach 2:
The semiconductor substrate is divided into two distinct functional layers: a first semiconductor element layer on the front surface and a second semiconductor element layer on the back surface. Each layer can be independently designed and optimized for specific functions, allowing parallel operation and reducing inter-layer interference while maximizing space utilization.
2Volume of moving object
If multiple semiconductor layers are integrated vertically, then size is reduced, but signal delay between layers increases
Solution Approach 1:
Through vias are introduced as intermediary conductive structures that directly connect the first semiconductor element layer on the front surface with the second semiconductor element layer on the back surface. These through vias provide short, direct signal paths that minimize transmission distance and reduce signal delay, enabling efficient vertical communication between the two surfaces.
3Volume of moving object
If both surfaces of the semiconductor substrate are utilized for different functions, then size reduction is achieved, but manufacturing complexity increases
Solution Approach 1:
The semiconductor element layers are formed on both surfaces of the substrate in advance during the manufacturing process, before final assembly and packaging. The through vias are also prepared in advance to establish electrical connections between the two surfaces. This preliminary formation of all necessary structures simplifies subsequent assembly steps and reduces overall manufacturing complexity.
Data Source
AI summary
A semiconductor apparatus includes a semiconductor layer having a first surface and a second surface that is opposite to the first surface; a first wire structure on the first surface of the semiconductor layer; a second wire structure on the second surface of the semiconductor layer; a through via that extends through the semiconductor layer and is electrically connected to the first wire structure and the second wire structure; a first semiconductor element layer that is adjacent to the first surface of the semiconductor layer and in the semiconductor layer; and a second semiconductor element layer that is adjacent to the second surface of the semiconductor layer and in the semiconductor layer.