Double Spacer Structure for Floating Gate Capacitive Coupling
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Solution Overview
Problem
Nonvolatile semiconductor memory devices, such as flash memory, experience read errors due to capacitive coupling between floating gates, which affects data retention and retrieval accuracy.
Innovation Solution
The design includes a control gate line with an extending portion between adjacent floating gates, accompanied by first and second spacers to reduce capacitive coupling and increase the distance between the control gate and active regions, thereby minimizing leakage currents and read errors. The spacers are strategically placed on the sidewalls of the floating gates and the device isolation layer to enhance insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the control gate line is positioned close to the floating gates for compact design, then device area is reduced, but capacitive coupling between adjacent floating gates increases causing read errors
Solution Approach 1:
The patent introduces spacers as intermediary structures positioned between adjacent floating gates. These spacers act as mediators that physically separate the floating gates while maintaining the compact overall device layout, thereby reducing capacitive coupling without significantly increasing the device area.
Solution Approach 2:
The patent extends the control gate line in the vertical dimension (Z-direction) to overlap with the sidewalls of floating gates. This dimensional extension allows the control gate to maintain electrical connection while the spacers provide horizontal separation, effectively decoupling the horizontal and vertical spatial relationships.
2Reliability
If spacers are added to reduce capacitive coupling, then read error rate decreases, but device complexity increases
Solution Approach 1:
The patent divides the spacer structure into two distinct segments: first spacers formed on the sidewalls of floating gates, and second spacers formed on the sidewalls of the device isolation layer. This segmentation allows each spacer type to perform its specific function independently while collectively achieving the goal of reducing capacitive coupling.
Solution Approach 2:
The patent implements a nested spacer configuration where second spacers are positioned outside the first spacers, creating a layered protective structure. The first spacers are formed closer to the floating gates, while second spacers extend further outward, providing multi-level isolation.
3Object-generated harmful factors
If the distance between control gate and active region is increased to reduce leakage current, then leakage current decreases, but device area increases
Solution Approach 1:
The patent applies different spacer configurations at different locations: first spacers are positioned where leakage current is most critical (at the interface between control gate and active region), while second spacers provide additional isolation where capacitive coupling is strongest (between adjacent floating gates). This localized approach optimizes leakage suppression without uniform area expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively decreases read errors and suppresses leakage currents, ensuring reliable data storage and retrieval in nonvolatile memory devices by reducing capacitive coupling and maintaining electrical potential stability between floating gates.
Implementation Method 1
A capacitive coupling may exist between the floating gates of unit cells adjacent to each other along the direction in which the control gate extends. This capacitive coupling may cause a read error in an operation mode for selectively reading data stored in a unit cell.
Implementation Method 2
first spacers disposed on sidewalls of the adjacent ones of the floating gates, wherein each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer; and second spacers disposed between outer sidewalls of the first spacers and the extending portion of the control gate line
Data Source
AI summary
A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.