Self-Aligned Double Spacer Patterning for 32 nm Pitch Interconnects
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Solution Overview
Problem
As semiconductor devices continue to shrink, traditional photolithography equipment struggles to achieve the required smaller process windows due to limitations in manufacturing pitch, making it difficult to maintain precise spacing between device elements.
Innovation Solution
A self-aligned double spacer patterning process is employed, involving the deposition of multiple spacer layers over mandrels and hard mask layers, allowing for precise etching and patterning to achieve smaller feature sizes without exceeding the limits of current photolithography technology. This process includes the use of tri-layer photoresists and selective etching techniques to transfer patterns onto semiconductor device layers, enabling the formation of smaller pitch interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography equipment is used, then manufacturing process is simpler and costs are lower, but manufacturing precision deteriorates due to inability to achieve required smaller pitch
Solution Approach 1:
The patterning process is divided into multiple discrete steps: forming mandrels, depositing first spacers, depositing second spacers, and selective removal. This segmentation allows each step to be optimized independently, achieving the required pitch precision through cumulative effect rather than requiring a single high-precision step that would demand advanced lithography equipment.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structures by forming spacers on the sidewalls of mandrels. This vertical dimension multiplication allows the horizontal pitch to be determined by vertical spacer thickness, which can be controlled with atomic layer deposition precision rather than lithographic resolution.
2Length of moving object
If photolithography process window is reduced to achieve smaller dimensions, then device scaling is enabled, but manufacturing precision deteriorates due to approaching equipment limits
Solution Approach 1:
Mandrels serve as intermediary structures that define the initial pattern, while spacers serve as intermediary layers that transfer and refine the pattern dimensions. The spacer thickness, controlled by ALD, acts as an intermediary parameter that decouples the final pitch precision from the lithographic process window, allowing precise spacing even when feature sizes are reduced.
3Manufacturing precision
If advanced EUV lithography is used to achieve smaller pitch, then manufacturing precision improves, but device complexity increases and costs increase
Solution Approach 1:
The patent creates multiple copies of the pattern through self-aligned spacer formation. The first spacers are formed conformally on mandrels, then second spacers are formed conformally on first spacers, creating a multiplied pattern structure. This copying approach achieves fine pitch by replicating and scaling the pattern rather than directly writing it at the final resolution, enabling use of less advanced lithography equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the pitch of semiconductor device features, allowing for the use of more established lithography technologies like 193 nm immersion lithography, thereby reducing costs and increasing throughput while achieving 32 nm pitch interconnects, which would otherwise require more advanced and costly EUV lithography.
Implementation Method 1
forming a first spacer layer over the set of mandrels and the first hard mask layer
Implementation Method 2
forming a second spacer layer over the first spacer layer
Implementation Method 3
patterning the first spacer layer and the second spacer layer to form a mask pattern
Implementation Method 4
patterning the first hard mask layer using the mask pattern as a mask
Data Source
AI summary
Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.