Self-Aligned Double Spacer Patterning for Sub-Lithographic Precision

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Solution Overview

Problem

As semiconductor devices continue to shrink, traditional photolithography equipment struggles to achieve the desired spacing between elements, approaching the limits of its manufacturing capabilities, leading to challenges in creating smaller features with sufficient precision and accuracy.

Innovation Solution

A self-aligned double spacer patterning process is employed, involving multiple mask layers and spacer formations to pattern a target dielectric layer, allowing for the creation of smaller features and improved process windows by overcoming film deposition topography issues in dense line-pattern environments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional photolithography equipment is used, then manufacturing process is simple, but manufacturing precision deteriorates as device dimensions shrink below equipment capabilities

Engineering Contradiction:
Improvefeature spacing precisionVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patterning process is divided into multiple discrete steps: forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. Each step creates a portion of the final pattern, allowing complex pitch division to be achieved through sequential simpler operations rather than a single complex lithography step.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from planar 2D patterning to 3D multi-layer spacer formation. By utilizing vertical dimension with multiple spacer layers deposited on mandrels, the process achieves pitch division ratios (e.g., 1:4, 1:8) that would be impossible with traditional single-layer photolithography, effectively adding a dimensional degree of freedom to the patterning process.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If photolithography process window is reduced to achieve smaller features, then device miniaturization is enabled, but manufacturing reliability deteriorates

Engineering Contradiction:
Improvefeature sizeVSAvoidprocess window
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The spacer layers are self-aligned to the mandrels through conformal deposition, automatically defining their position and spacing. This self-alignment mechanism eliminates the need for separate alignment steps and reduces sensitivity to lithography process variations, thereby maintaining reliability while achieving smaller features.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The invention changes the controlling parameter from lithographic resolution (which has fundamental limits) to thin film deposition thickness (which can be precisely controlled at atomic levels). By using atomic layer deposition or chemical vapor deposition to control spacer thickness, the process achieves precision beyond the diffraction limit of optical lithography.

Inventive Principle:
Principle #35Parameter changes

3Length of moving object

If pitch is reduced below photolithography capabilities, then device scaling is achieved, but manufacturing accuracy deteriorates

Engineering Contradiction:
ImprovepitchVSAvoidspacing accuracy
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

Mandrels serve as intermediary structures that define the positions of spacer features. The mandrels act as templates upon which spacers are conformally deposited, allowing precise spacing to be defined by the mandrel positions and spacer thickness rather than direct lithographic patterning. This intermediary approach enables sub-lithographic pitch accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10056258B2Self-aligned double spacer patterning process
Publication Date: 2018.08.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10056258B2 patent drawing
  • US10056258B2 patent drawing
  • US10056258B2 patent drawing

AI summary

A method includes forming a mask layer over a target layer. A merge cut feature is formed in the mask layer. A first mandrel layer is formed over the mask layer and the merge cut feature. The first mandrel layer is patterned to form first openings therein. First spacers are formed on sidewalls of the first openings. The first openings are filled with a dielectric material to form plugs. The first mandrel layer is patterned to remove portions of the first mandrel layer interposed between adjacent first spacers. The merge cut feature is patterned using the first spacers and the plugs as a combined mask. The plugs are removed. The mask layer is patterned using the first spacers as a mask. The target layer is patterned, using the mask layer and the merge cut feature as a combined mask, to form second openings therein.