Double Spacer Process for Semiconductor Pattern Density

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Solution Overview

Problem

In advanced semiconductor integrated circuit (IC) manufacturing, the scaling down process increases complexity and reduces pattern density due to equal etching rates in lateral and vertical directions, leading to increased line end-to-end distance and pitch, which is challenging to manage with traditional spacer techniques.

Innovation Solution

A double spacer process is employed, where the thickness of spacers is adjusted to tune the final pattern's pitch and line-to-line spacing without the need for photoresist trimming, allowing for flexible control of the end-to-end distance and reducing the line end-to-end distance, thereby increasing pattern density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional spacer techniques are used with equal etching rates in lateral and vertical directions, then the etching process is simple and uniform, but the line end-to-end distance and pitch increase, reducing pattern density

Engineering Contradiction:
Improvepattern densityVSAvoidline end-to-end distance
Core Design Contradiction:
Manufacturing precisionVSLength of moving object

Solution Approach 1:

The patent divides the single spacer formation process into two separate spacer formation steps. First spacer is formed on mandrel lines, then second spacer is formed on the first spacer. This segmentation allows independent control of each spacer's thickness, enabling precise tuning of the final pattern pitch and line-to-line spacing without increasing line end-to-end distance excessively.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic adjustability by allowing different thicknesses for the first and second spacers. The thickness of each spacer can be independently tuned to achieve the desired final pattern dimensions. This dynamic parameter control enables flexible optimization of pattern density while maintaining manufacturability.

Inventive Principle:
Principle #15Dynamics

2Manufacturing precision

If photoresist trimming is used to reduce pitch, then the final pattern pitch can be reduced, but the process complexity and manufacturing costs increase

Engineering Contradiction:
Improvepitch controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts and removes the photoresist trimming step from the process flow. Instead of trimming photoresist to reduce pitch, the patent forms two spacers that self-align to the mandrel lines, achieving pitch reduction without the need for additional trimming operations. This eliminates the complexity and cost associated with photoresist trimming while maintaining precise pitch control.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The double spacer process is self-aligning, where the second spacer automatically positions itself relative to the first spacer and mandrel lines. This self-service mechanism eliminates the need for complex alignment and trimming operations, reducing process complexity while achieving the desired pitch reduction.

Inventive Principle:
Principle #25Self-service

3Productivity

If scaling down is implemented to increase functional density, then production efficiency increases and costs decrease, but processing complexity increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

By segmenting the spacer formation into two independent steps with different thicknesses, the patent enables precise control of final pattern dimensions at scaled-down nodes. This segmentation allows the process to accommodate smaller feature sizes while maintaining manufacturing control, thereby supporting continued scaling down to increase functional density without proportionally increasing processing complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10049919B2Semiconductor device including a target integrated circuit pattern
Publication Date: 2018.08.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10049919B2 patent drawing
  • US10049919B2 patent drawing
  • US10049919B2 patent drawing

AI summary

A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.