Double Trench Epitaxy for FinFET Defect Management
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Solution Overview
Problem
Conventional methods for forming semiconductor fins in FinFET devices result in strain-induced crystal lattice defects and patterning deformities, such as tapering and roughness, which degrade device performance due to the integration of dissimilar semiconductor materials like III-V compounds on silicon substrates.
Innovation Solution
A method involving double trench epitaxy is employed, where two separate aspect ratio trapping processes are used in lower and upper trenches to trap crystalline defects, and an epitaxial layer is grown within the upper trench to form a fin, minimizing sidewall roughness and defect propagation by precise removal of dielectric layers adjacent to the epitaxial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form fins in FinFET devices, then manufacturing process is simpler, but fin patterning deformations such as tapering and roughness occur
Solution Approach 1:
The fin formation process is segmented into two separate trench structures: a lower trench for defect trapping and an upper trench for fin formation. This segmentation allows the defect trapping function to be separated from the fin formation function, enabling high-precision fin patterning while maintaining manufacturing feasibility through modular process steps.
Solution Approach 2:
The lower trench acts as an intermediary structure between the substrate and the upper trench. It traps crystalline defects that would otherwise propagate to the fin region, serving as a mediator that protects the fin formation area from defects while allowing the epitaxial growth process to proceed in the upper trench.
2Adaptability or versatility
If dissimilar semiconductor materials are integrated, then device functionality is enhanced, but strain-induced crystal lattice defects increase
Solution Approach 1:
The strain-induced crystalline defects generated by integrating dissimilar semiconductor materials are converted from harmful factors into beneficial trapped defects. The lower trench structure captures these defects, preventing them from propagating to the fin region, thereby transforming the material mismatch problem into a controlled defect management solution.
Solution Approach 2:
Crystalline defects are extracted from the potential defect propagation path by confining them within the lower trench structure. This extraction removes the harmful effect of defects from the fin formation region, allowing high-quality fin structures to be formed despite the use of dissimilar semiconductor materials.
3Manufacturing precision
If conventional fin formation methods are used, then process time is reduced, but fin sidewall roughness and tapering increase
Solution Approach 1:
The lower trench is formed and configured before the upper trench epitaxial growth. This preliminary action prepares the defect trapping structure in advance, ensuring that when the fin is formed in the upper trench, the defect management system is already in place, enabling high-precision fin formation without requiring additional corrective steps.
Solution Approach 2:
The problem of fin sidewall quality is addressed by adding a vertical dimension to the defect management strategy. Instead of relying solely on horizontal patterning control, the solution introduces a vertical lower trench structure that captures defects in the depth dimension, thereby improving fin sidewall quality without compromising formation efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces crystalline lattice defects and sidewall roughness, enhancing the performance of semiconductor fins by preventing defect propagation and maintaining fin integrity during processing.
Implementation Method 1
forming an epitaxial layer on the first upper surface of the substrate and on the upper surface of the one or more remaining portions of the first dielectric layer, the epitaxial layer filling the lower trench and the one or more upper trenches
Data Source
AI summary
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.