Double Trench Isolation for Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor devices face challenges in junction termination and isolation, particularly in integrating super-MOS devices with other devices in smart power platforms, where symmetry breaking at the periphery affects reverse voltage capability, requiring improved termination structures.
Innovation Solution
A semiconductor device utilizing a double trench isolation approach with a first trench extending towards a buried layer and a second deep trench through the buried layer, reducing the isolation distance and area needed for electrical isolation, allowing for greater integration and improved performance parameters like reduced on-resistance (Ron).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single trench is used for isolation, then the device structure is simple, but the isolation distance must be large (15 μm) to ensure blocking capability
Solution Approach 1:
The isolation structure is divided into two separate trenches: a first trench extending towards the buried layer and a second deep trench extending through the buried layer. This segmentation allows each trench to perform a specific isolation function, enabling the total isolation distance to be reduced from 15 μm to 3 μm while maintaining adequate blocking capability through the combined effect of both trenches.
Solution Approach 2:
The isolation approach transitions from a single horizontal dimension (one trench) to multiple vertical dimensions (two trenches at different depths). The first trench provides isolation in the upper region while the second deep trench provides isolation in the lower region through the buried layer, creating a multi-layered isolation architecture that reduces the required lateral isolation distance.
2Reliability
If a large isolation distance is used, then blocking capability is ensured, but the device area increases reducing integration density
Solution Approach 1:
The blocking capability is segmented between two trenches at different depths. The first trench provides blocking in the upper active region while the second deep trench provides blocking in the lower region through the buried layer. This segmentation allows the lateral isolation distance to be reduced to 3 μm while the vertical depth of the trenches provides the necessary blocking capability, thereby reducing device area without sacrificing reliability.
Solution Approach 2:
The blocking function is moved from a primarily lateral dimension to a vertical dimension. Instead of relying on a large lateral distance (15 μm) for blocking, the solution uses vertical depth by etching two trenches to different depths, with the second trench extending through the buried layer. This dimensional transition enables compact lateral spacing (3 μm) while maintaining adequate blocking through vertical isolation.
3Productivity
If the isolation distance is reduced, then integration density improves, but junction termination becomes more difficult
Solution Approach 1:
The junction termination function is segmented between two trenches: the first trench handles termination in the upper active region and the second deep trench handles termination in the lower region through the buried layer. This segmentation allows the lateral spacing between cells to be reduced to 3 μm, improving integration density, while each trench independently provides the necessary termination depth for manufacturing feasibility.
Solution Approach 2:
The junction termination approach transitions from lateral extension to vertical depth. Instead of requiring large lateral distances for termination, the solution uses vertical depth by etching trenches to different depths. The first trench provides termination depth in the upper region while the second deep trench provides termination depth through the buried layer, enabling compact lateral spacing (3 μm) while maintaining adequate termination depth for manufacturing.
Data Source
AI summary
Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.