Double-Via Backside Contacts for Stacked Transistor Short Isolation
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Solution Overview
Problem
Existing techniques for connecting bottom source/drains in stacked field-effect transistors to the back-end-of-line wiring are challenging, especially as device dimensions shrink, leading to increased risks of shorting between vias.
Innovation Solution
A semiconductor structure featuring a double via with a dividing cut that splits the via into two halves, allowing each half to connect directly to a bottom source/drain without shorting, while enabling close proximity without electrical contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to connect bottom source/drains to BEOL, then electrical connection is achieved, but the risk of shorting between vias increases as device dimensions shrink
Solution Approach 1:
The via structure is divided into two separate halves by introducing a dividing cut, which physically separates the via into independent regions. This segmentation prevents electrical shorting between adjacent vias while maintaining individual electrical connections to bottom source/drains, directly resolving the shorting risk issue in miniaturized devices
Solution Approach 2:
A dielectric material is introduced as an intermediary substance filling the dividing cut between the two via halves. This dielectric layer acts as an electrical insulator that prevents shorting while allowing both via halves to maintain their electrical connections, solving the reliability issue without increasing device footprint
2Reliability
If conventional via techniques are used, then connection to bottom source/drains is achieved, but device placement flexibility is limited due to larger required spacing
Solution Approach 1:
By segmenting the via into two halves with a dividing cut, the structure allows closer spacing between adjacent devices while maintaining reliable electrical connections. The segmented design reduces the required spacing compared to conventional via techniques, enabling greater device placement flexibility in scaled devices
Solution Approach 2:
The dividing cut introduces localized insulation only where needed between via halves, rather than requiring uniform spacing throughout the device structure. This local quality approach allows dense device placement in critical areas while maintaining connection reliability, enhancing overall device placement flexibility
3Productivity
If via size is reduced to accommodate smaller devices, then device density increases, but the contact surface area between source/drains and contacts decreases
Solution Approach 1:
The dividing cut creates two distinct via halves, each with its own contact interface to bottom source/drains. This segmentation effectively doubles the contact surface area within the same via footprint, maintaining sufficient electrical contact area even as overall via dimensions are reduced for higher device density
Solution Approach 2:
The dividing cut introduces a new dimensional feature within the via structure, creating vertical and lateral contact surfaces. This dimensional complexity increases the effective contact surface area without increasing the via's planar footprint, enabling reduced via size while maintaining contact quality
Data Source
AI summary
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a device layer having a first top source/drain (S/D), a second top S/D, a first bottom S/D, and a second bottom S/D. The semiconductor structure may further include a first direct back side contact connected to the first bottom S/D, a second direct back side contact connected to the second bottom S/D, and a double via. The double via may include a first half connecting a front side of the device layer to the first direct back side contact, and a second half connecting the front side to the second direct back side contact. The double via may also include a dividing cut splitting the first half of the double via from the second half of the double via.