Double Wrapping Firmware Verification for Boot Latency
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Solution Overview
Problem
Memory sub-systems face latency issues during boot-up due to the time required for verifying the integrity of firmware images, especially when using traditional cryptographic verification methods that can be vulnerable to corruption or hacking.
Innovation Solution
Implementing a verification manager that utilizes both symmetric and asymmetric cryptographic procedures to verify the integrity of firmware images, allowing for faster boot-up by initially using symmetric cryptographic signatures and falling back to asymmetric signatures if necessary, thereby maintaining security while reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional asymmetric cryptographic verification is used to verify firmware image integrity, then security is improved, but boot-up latency increases
Solution Approach 1:
The verification process is segmented into two distinct stages: a fast symmetric cryptographic verification performed first during boot-up, and a slower asymmetric cryptographic verification performed later. This segmentation allows the system to achieve quick initial verification while maintaining the option for more thorough verification when needed, thus resolving the contradiction between security and boot-up speed.
Solution Approach 2:
A symmetric cryptographic signature is applied preliminarily to the firmware image during manufacturing, enabling fast verification during boot-up. This preliminary action provides immediate security verification without the computational overhead of asymmetric cryptography, while the asymmetric signature remains available for later comprehensive verification if required.
2Reliability
If only asymmetric cryptographic signatures are used for firmware verification, then security against corruption and hacking is improved, but device complexity increases
Solution Approach 1:
The verification system is segmented into two independent verification paths: symmetric cryptographic verification and asymmetric cryptographic verification. Each path can operate independently, allowing the system to use the simpler symmetric verification for routine checks while maintaining the asymmetric verification capability for enhanced security scenarios, thus managing device complexity effectively.
Solution Approach 2:
The verification manager is designed with multi-functionality to handle both symmetric and asymmetric cryptographic verifications. This universal approach allows a single verification system to provide multiple levels of security verification, reducing the need for separate dedicated verification systems and thereby managing device complexity while maintaining high security standards.
Data Source
AI summary
Methods, systems, and devices for double wrapping for verification are described. In some cases, a memory subsystem can receive a firmware image for the memory subsystem where the firmware image is signed with a first signature according to a first signing procedure. The memory subsystem can then verify an integrity of the firmware image based on the first signing procedure. After verifying the integrity of the firmware image, the memory subsystem can then generate a second signature for the firmware image based on a second signing procedure different from the first signing procedure. The memory subsystem can then write the second signature to the firmware image. The memory subsystem can then perform a verification process to verify the integrity of the firmware image based on one or both of the first signing procedure or the second signing procedure. In this case, a first verification time is associated with the first signing procedure and is greater than a second verification time associated with the second signing procedure.