Double-Write Controller for NAND Memory Error Suppression
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Solution Overview
Problem
Nonvolatile memory devices, such as NAND-type flash memory devices, face reliability degradation due to cell-to-cell interference and high error rates when using multi-level cell techniques and advanced process techniques, leading to increased write errors and reduced endurance.
Innovation Solution
A semiconductor system with a write buffer and a controller that performs a double-write operation, writing data into a memory circuit under specific conditions to reduce error rates and maintain performance, utilizing error correction codes and multiple write routes to manage data storage and retrieval efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double-write operation is performed to suppress write errors, then reliability is improved, but the number of accesses to memory cells increases causing degradation of endurance
Solution Approach 1:
A write buffer is introduced as an intermediary component between the host and the memory circuit. The buffer temporarily stores write data and allows the controller to manage double-write operations selectively based on buffer status, thereby reducing direct access frequency to memory cells while maintaining error suppression capabilities
Solution Approach 2:
Write data is preliminarily stored in the write buffer before being written to the memory circuit. This preliminary action allows the controller to evaluate buffer conditions and determine whether double-write is necessary, preventing unnecessary repeated accesses to memory cells and preserving endurance
2Quantity of substance
If multi-level cell techniques are used to increase integration density, then the number of bits per cell increases, but cell-to-cell interference occurs degrading reliability
Solution Approach 1:
The write operation is segmented into multiple independent stages: data reception, buffer storage, error correction encoding, conditional double-write execution, and memory programming. This segmentation allows selective application of double-write only when buffer conditions warrant it, mitigating the reliability degradation caused by MLC cell-to-cell interference
3Length of moving object
If advanced process techniques are used to reduce minimum feature size, then integration density increases, but data errors occur more easily
Solution Approach 1:
The controller implements feedback mechanisms by monitoring write buffer status and error conditions. Based on this feedback, the controller dynamically adjusts whether to perform double-write operations, creating a closed-loop system that adapts to actual error conditions rather than applying double-write universally, thus maintaining reliability without excessive wear
Data Source
AI summary
A semiconductor system includes a controller. The controller is configured to have a write buffer that stores first write data outputted from a host before the first write data is written into a memory circuit. The controller is configured to write the first write data stored in the write buffer into the memory circuit under a first condition and configured to double-write the first write data stored in the write buffer into the memory circuit under a second condition.