Downgraded DRAM Module Using Non-Multiplexed Address Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in memory module manufacturing is the wasteful discarding of DRAM chips with single defects, as current testing methods fail to exhaustively identify defects, leading to the need for a process to utilize downgraded memory chips effectively.
Innovation Solution
The implementation of a memory module manufacturing process that allows the use of downgraded DRAM chips by dividing them into logical halves or quadrants, using jumpers to selectively access functional parts, and integrating this with a manufacturing flowchart to identify and utilize good quadrants or halves for reduced-capacity modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If current testing methods are used, then manufacturing cost is reduced, but defective chips are discarded wastefully
Solution Approach 1:
The patent divides a defective DRAM chip into multiple functional segments (halves or quadrants) based on defect location. By identifying which portions of the chip are still functional, the system can utilize only the good segments, thereby reducing waste while maintaining manufacturing cost-effectiveness.
Solution Approach 2:
The patent applies local quality by treating different regions of the chip differently based on their functional status. Good quadrants are activated and made accessible through specific address line configurations, while defective quadrants are disabled, allowing the chip to function with reduced but still useful capacity.
2Measurement precision
If exhaustive testing is performed, then defect detection precision is improved, but testing time and cost increase
Solution Approach 1:
The patent implements partial testing by focusing testing efforts on identifying defect locations rather than exhaustively testing every memory cell. By detecting defects and then using address line multiplexing to access only functional quadrants, the system achieves sufficient defect detection precision without the time and cost burden of complete exhaustive testing.
3Adaptability or versatility
If downgraded chips are utilized, then chip usage efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces address line multiplexing as an intermediary mechanism to manage the complexity of accessing downgraded chip segments. By using existing address lines in a multiplexed fashion to selectively access different quadrants based on defect patterns, the system achieves high chip usage efficiency without requiring entirely new complex addressing infrastructure.
Data Source
AI summary
A downgraded memory module has downgraded DRAM chips soldered to its substrate. The downgraded DRAM chips have a defective memory cell in a logical quadrant of the memory. A physical MSB is a row address present on a non-downgraded DRAM of size S but not used on a downgraded DRAM size S/2. The physical MSB and a second address pin are non-multiplexed address pins that do not carry column addresses. The physical MSB and the second address pin logically divided the DRAM into quadrants. Two good quadrants without defects are selected, and jumpers on the memory module drive the physical MSB and the second address pin with signals that select only these two quadrants and disable access to quadrants containing defects. DRAM chips can be marked or sorted into bins for combinations of good quadrants. Downgraded memory modules have all DRAM chips from the same bin that share jumper settings.