Downlink Data Processing Accelerator for 5G Terminal CPU Offload

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Solution Overview

Problem

Current 5G communication systems face increased CPU resource demands and power consumption due to high transmission rates, leading to higher costs and DDR bandwidth requirements in processing downlink data protocols like MAC, RLC, PDCP, and SDAP, which are mainly handled by software on the CPU.

Innovation Solution

Incorporating a downlink data processing accelerator, specifically a hardware-based solution that performs MAC, RLC, and PDCP layer processing, reducing the CPU's workload and leveraging ASICs for efficient data handling, thereby offloading software processing and minimizing DDR bandwidth needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software-based processing is used for downlink data protocols (MAC, RLC, PDCP, SDAP), then implementation flexibility is maintained, but CPU resource consumption and power consumption increase significantly

Engineering Contradiction:

Improveimplementation flexibilityVSAvoidCPU resource consumption and power consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent divides the data processing function into separate hardware modules: a physical layer decoding accelerator for PHY layer processing and a downlink data processing accelerator for MAC/RLC/PDCP layer processing. This segmentation allows each module to be optimized independently, with the downlink data processing accelerator handling protocol processing in hardware to reduce CPU workload while maintaining implementation flexibility through configurable hardware architectures.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces software-based mechanical processing with hardware-based acceleration. The downlink data processing accelerator uses hardware circuits to perform MAC, RLC, and PDCP layer processing operations that were previously executed through software instructions on the CPU. This substitution dramatically reduces CPU resource consumption and power consumption while maintaining processing functionality.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If high transmission rates are implemented in 5G systems, then data throughput is improved, but CPU resource demands and processing complexity increase

Engineering Contradiction:

Improvedata throughputVSAvoidCPU resource demands and processing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the protocol processing functions (MAC, RLC, PDCP) from the CPU and implements them in a dedicated downlink data processing accelerator. This extraction removes the processing complexity from the CPU, allowing high throughput operation without proportionally increasing CPU resource demands. The accelerator handles the complex protocol processing independently while the CPU focuses on higher-layer functions.

Inventive Principle:

Principle #2Taking out (Extraction)

3Use of energy by moving object

If hardware-based acceleration is introduced for downlink data processing, then processor resource consumption and power consumption are reduced, but device complexity increases

Engineering Contradiction:

Improveprocessor resource consumption and power consumptionVSAvoiddevice complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The downlink data processing accelerator is designed as a multi-functional hardware module that handles MAC layer control elements, RLC layer protocol data units, and PDCP layer service data units through a unified architecture. This multi-functionality consolidates multiple processing tasks into a single hardware component, reducing overall device complexity compared to having separate dedicated hardware for each protocol layer while maintaining low processor resource consumption and power consumption.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12261694B2Terminal device based on downlink data processing accelerator

Publication Date: 2025.03.25 SPREADTRUM COMMUNICATION (SHANGHAI) CO LTD

AI summary

A terminal device includes: a PHY decoding accelerator, a downlink data processing accelerator and a CP; where the PHY decoding accelerator is configured to decode and CRC check received downlink data, and send a correctly decoded transport block (TB) to the downlink data processing accelerator; the downlink data processing accelerator performs processing operations of a MAC layer, a RLC layer, and a PDCP layer on the TB to obtain an MAC CE, an RLC control PDU, an RLC TMD PDU, a PDCP control PDU and a PDCP data SDU, and outputs to the CP; and the CP processes the MAC CE, the RLC control PDU, the RLC TMD PDU, the PDCP control PDU and the PDCP data SDU.