Downlink Slot Structure Relaxing Processing Timeline
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Solution Overview
Problem
In wireless communication systems, the short turnaround time required for processing downlink subframes can strain processing resources due to the need for low latency and flexible numerology, leading to processing bottlenecks, especially when delayed data processing is involved.
Innovation Solution
The proposed solution involves a slot structure that relaxes the processing timeline by frequency division multiplexing control information with demodulation reference signals or user data in the initial symbol, allowing for delayed data processing and buffering, and employing payload pre-tapering techniques to reduce processing load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If flexible numerology with short symbol duration is used to reduce latency, then communication latency is reduced, but processing resources are strained and processing bottlenecks occur
Solution Approach 1:
The patent segments the downlink slot into distinct regions: a first region containing control information and reference signals, and a second region containing data. This segmentation allows the receiving device to process control information separately from data, reducing the processing burden in the time-critical path and alleviating processing resource strain while maintaining low latency.
Solution Approach 2:
The patent places control information and demodulation reference signals in the first symbol before data transmission. This preliminary action allows the receiving device to decode control information and prepare processing resources in advance, reducing the processing timeline pressure during the short turnaround time enabled by flexible numerology.
2Loss of time
If control information is placed in the first symbol with data, then latency is reduced, but processing load increases causing bottlenecks
Solution Approach 1:
The patent applies local quality by assigning different processing characteristics to different regions of the downlink slot. The first symbol containing control information is processed with higher priority and different resource allocation than the data region, allowing the device to manage processing load efficiently by focusing resources on time-critical control information decoding first.
3Device complexity
If delayed data processing is implemented to relax processing timeline, then processing resources are protected, but processing bottlenecks occur after buffering delay
Solution Approach 1:
The patent performs preliminary actions by placing control information and reference signals in the first symbol before data. This allows the receiving device to prepare processing resources, allocate buffers, and configure demodulation parameters in advance, so that when data processing occurs after buffering delay, the processing load is already optimized and bottlenecks are avoided.
Data Source
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AI summary
Aspects of the disclosure provide a slot structure (e.g., the arrangement of channels and pilot signals within a slot) that can relax the processing timeline for a wireless communication device. For example, in the first or initial symbol of a slot, control information may be frequency division multiplexed (FDM) with a demodulation reference signal (DMRS) or with user data. In some cases, delayed-processing data may be sampled, and the samples may be buffered at the receiving device, for processing later, after control information needed to process the data has been received and processed. Further aspects provide for payload pre-tapering. That is, when a device delays the processing of data bits, this can cause a processing bottleneck after that buffering delay. By virtue of various pre-tapering techniques described herein, the processing load needed to process the delayed-processing data can be reduced. Other aspects, embodiments, and features are also claimed and described.