Downset Lead IC Package Solder Bump Control
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Solution Overview
Problem
Conventional techniques for soldering flip chips in integrated circuit packages face challenges in precisely controlling solder bump height and spacing, leading to issues like excessive wetting, reduced collapse height, poor planarity, solder overflow, and insufficient lead registration, which affect the performance and manufacturing of integrated circuit packages.
Innovation Solution
The use of downset terminal leads with a planar recessed lead surface, which provides a controlled adhesion and cohesion for solder bumps, restricting their spread and regulating their height, and includes terminal and paddle locking features for improved registration and encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional reflow solder techniques are used to solder flip chips to conductor patterns, then soldering can be performed, but solder bump height cannot be closely controlled and solder overflow occurs
Solution Approach 1:
The patent applies preliminary action by forming a solder resist pattern on the substrate before depositing solder material. This pre-established resist pattern defines the boundaries and geometry of solder bumps before they are formed, thereby controlling solder bump height and preventing solder overflow during the reflow process. The solder resist pattern acts as a preliminary structure that constrains the molten solder within desired boundaries.
2Reliability
If solder is deposited to achieve proper chip positioning, then electrical connection is established, but stress relief during thermal cycles is compromised
Solution Approach 1:
The patent applies local quality by creating a solder resist pattern with varying properties in different regions. The resist pattern includes areas with different thicknesses and material compositions to provide both mechanical support for chip positioning and stress relief during thermal cycling. This localized variation in material properties allows the structure to simultaneously achieve precise positioning and thermal stress management.
3Area of stationary object
If conductor patterns are composed of numerous closely spaced conductors to accommodate fine terminal patterns, then area arrays can be formed, but soldering precision requirements increase significantly
Solution Approach 1:
The patent introduces a solder resist pattern as an intermediary element between the conductor patterns and the solder bumps. This resist pattern serves as a mediator that defines the geometry and position of solder bumps, thereby relaxing the direct precision requirements between closely spaced conductors. The intermediary resist layer absorbs positioning tolerances and ensures accurate solder deposition even when conductors are closely spaced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances wetting, collapse height, planarity, and eliminates solder overflow, resulting in improved package performance and manufacturing efficiency by controlling solder bump height and spacing.
Implementation Method 1
provides a controlled adhesion and cohesion for solder bumps, restricting their spread and regulating their height
Implementation Method 2
provides a controlled adhesion and cohesion for solder bumps, restricting their spread and regulating their height
Implementation Method 3
includes terminal and paddle locking features for improved registration and encapsulation
Data Source
AI summary
An integrated circuit package system includes an integrated circuit package having a downset terminal lead, a planar recessed lead surface of the downset terminal lead, and an attached integrated circuit over the planar recessed lead surface.