Downshifting Multi-Level Memory Cells to Manage Capacity Reduction

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Solution Overview

Problem

Modern memory sub-systems face challenges in managing capacity reductions due to device failures, leading to inefficient waste of remaining memory devices and increased costs, as existing fault tolerance mechanisms are limited in handling failures and can affect performance and reliability.

Innovation Solution

The memory sub-system detects failures, communicates with the host system to manage capacity reductions, allowing the system to operate at a reduced capacity by reallocating storage and preserving data, thereby extending the system's operational duration and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing fault tolerance mechanisms are used to handle memory device failures, then system reliability is maintained, but remaining memory devices are wasted and capacity is reduced

Engineering Contradiction:
Improvesystem reliabilityVSAvoidmemory device waste
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent changes the operational parameters of remaining memory devices by downshifting multi-level memory cells from higher density modes (e.g., TLC, QLC) to lower density modes (e.g., SLC, MLC). This parameter change allows the system to maintain reliability through error correction while preserving capacity by operating remaining devices in more robust, error-resistant modes

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system dynamically adjusts the operational mode of memory devices based on failure detection. When failures are detected, the system transitions from static high-capacity operation to dynamic adaptive operation where remaining devices are reconfigured with adjusted parameters to maintain both reliability and optimal resource utilization

Inventive Principle:
Principle #15Dynamics

2Duration of action of stationary object

If memory sub-system operates at reduced capacity due to failures, then system lifespan is extended, but performance and reliability may be affected

Engineering Contradiction:
Improvesystem lifespanVSAvoidsystem reliability
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

The patent applies parameter changes by downshifting memory cell operation modes to achieve more conservative, error-resistant operational parameters. This allows the system to extend lifespan through careful management of remaining devices while maintaining reliability through the inherent error-correcting properties of the downshifted modes

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If multi-level memory cells are downshifted to manage capacity reduction, then remaining memory capacity is preserved, but write endurance is reduced

Engineering Contradiction:
Improveremaining memory capacityVSAvoidwrite endurance
Core Design Contradiction:
Quantity of substanceVSDuration of action of moving object

Solution Approach 1:

The patent deliberately changes the operational parameters of memory cells from high-density modes to low-density modes. This parameter change preserves remaining capacity by making it accessible while accepting reduced write endurance as a trade-off, managed through careful selection of downshift targets and operational policies

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11520500B2Managing capacity reduction when downshifting multi-level memory cells
Publication Date: 2022.12.06 MICRON TECHNOLOGY INC
  • US11520500B2 patent drawing
  • US11520500B2 patent drawing
  • US11520500B2 patent drawing

AI summary

A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.